IP Library Granted Patent US 9,111,897
Granted Patent B2
US 9,111,897 · App. 13/716,859 · Granted Aug 18, 2015

Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices

Inventors: Jung-Geun Jee (Seoul, KR); Jin-Gyun Kim (Yongin-si, KR); Ji-Hoon Choi (Seongnam-si, KR); Ki-Hyun Hwang (Seongnam-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L21/36C23C16/24H01L21/0245H01L21/0262H01L21/02381H01L21/02488H01L21/02494H01L21/02532H01L21/02576H01L21/02579H01L21/02595H01L21/02639H01L21/28525H01L21/28556H01L21/76876H01L21/76877H01L27/10888H01L27/11582H01L29/66666
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Quick Facts
Patent No.
US 9,111,897
App. No.
13/716,859
Granted
Aug 18, 2015
Kind
B2
Abstract

A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

Claims (37)

1. A method of forming a polysilicon layer, comprising:

providing a silicon precursor onto an object loaded in a process chamber to form a seed layer, wherein the silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor, and wherein the nitrogen containing silicon precursor and the chlorine containing silicon precursor are adsorbed directly on the object; and

providing a silicon source on the seed layer.

2. The method of claim 1 , wherein the nitrogen containing silicon precursor includes at least one selected from the group consisting of Bis(ethylmethylamino)silane (BEMAS), Bis(diethylamino)silane (BDEAS), Bis(dimethylamino)silane (BDMAS), tris(dimethylamino)silane (Tris-DMAS), tetrakis(dimethylamino)silane (TDMAS), tris(ethylmethylamino)silane (Tris-EMAS), Diethylaminosiliane (DEAS), Bis(tertybutylamino)silane (BTBAS) and Di-Isopropyl-Amino-Silane (DIPAS).

3. The method of claim 1 , wherein the chlorine containing silicon precursor includes at least one selected from the group consisting of dichlorosilane (SiCl 2 H 2 ), trichlorosilane (SiCl 3 H), tetrachlorosilane (SiCl 4 ) and hexachlorodisilane (Si 2 Cl 6 ).

4. The method of claim 1 , wherein the silicon source includes at least one selected from the group consisting of silane (SiH 4 ), disilane (Si 2 H 6 ) and trisilane (Si 3 H 8 ).

5. The method of claim 1 , wherein the process chamber includes an atomic layer deposition (ALD) process chamber.

6. The method of claim 1 , wherein the providing of the silicon precursor onto the object loaded in the process chamber to form the seed layer comprises:

providing the nitrogen containing silicon precursor onto the object loaded in the process chamber to form a preliminary seed layer; and

providing the chlorine containing silicon precursor on the preliminary seed layer to form the seed layer.

7. The method of claim 6 , further comprising: performing a first purge process and a heat treatment after forming the preliminary seed layer.

8. The method of claim 7 , wherein nitrogen atoms or silicon atoms of the nitrogen containing silicon precursor are activated by the first purge process and the heat treatment.

9. The method of claim 8 , further comprising: performing a second purge process after providing the chlorine containing silicon precursor, wherein —N—Si—Cl or —Si—Cl groups that are attached to silicon atoms of the seed layer are removed by the second purge process.

10. The method of claim 9 , wherein the second purge process reduces the seed layer to a single atomic layer structure.

11. The method of claim 1 , wherein the providing of the nitrogen containing silicon precursor and the providing of the chlorine containing silicon precursor are simultaneously performed.

12. The method of claim 6 , wherein the forming of the preliminary seed layer and the forming of the seed layer are repeatedly performed.

13. The method of claim 1 , wherein the object includes a substrate and an insulation layer formed thereon, and wherein the insulation layer includes an opening therethrough such that a top surface of the substrate is exposed.

14. The method of claim 13 , wherein the insulation layer has a multi-layered structure including a silicon oxide layer and a silicon nitride layer.

15. The method of claim 1 , wherein an impurity gas is provided together with the silicon source.

16. A method of manufacturing a semiconductor device, comprising:

forming a plurality of sacrificial layers and a plurality of insulating interlayers alternately and repeatedly on an object;

forming a hole through the sacrificial layers and the insulating interlayers, wherein the substrate is exposed by the hole;

providing a nitrogen containing silicon precursor to form a preliminary seed layer on an inner wall of the hole;

providing a chlorine containing silicon precursor on the preliminary seed layer to form a seed layer;

providing a silicon source on the seed layer to form a polysilicon channel on the inner wall of the hole;

removing the sacrificial layers to form grooves between the insulating interlayers; and

forming a gate structure in each groove,

wherein the nitrogen containing silicon precursor and the chlorine containing silicon precursor are adsorbed directly on the inner wall of the hole.

17. The method of claim 16 , wherein the gate structure includes a tunnel insulation layer, a charge trapping layer, a blocking layer and a gate electrode sequentially stacked in each groove.

18. A method for forming a polysilicon layer pattern comprising:

forming an insulation layer on a substrate;

forming an opening in the insulation layer by removing a portion of the insulation layer, wherein a top surface of the substrate is exposed by the opening;

forming a seed layer in the opening by providing a silicon precursor onto an object loaded in a process chamber, wherein the silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor, and the nitrogen containing silicon precursor and the chlorine containing silicon precursor are adsorbed directly on the object;

providing a silicon source on the seed layer to form a polysilicon layer; and

planarizing an upper portion of the polysilicon layer to form a polysilicon layer pattern in the opening.

19. The method of claim 18 , wherein the polysilicon layer pattern is formed on an inner wall of the opening and the exposed top surface of the substrate and the method further comprising: forming a filling layer pattern on the polysilicon layer pattern to fill a remaining portion of the opening.

20. The method of claim 18 , wherein the polysilicon layer pattern fills substantially the entire opening and contacts with an impurity region disposed at an upper portion of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: JEE, JUNG-GEUN; KIM, JIN-GYUN; CHOI, JI-HOON; HWANG, KI-HYUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029482/0517 →
Priority Claims (1)
KR 10-2012-0038398 · Apr 13, 2012 · national
Continuity (1)
Related Publication 20130273704A1 · Oct 17, 2013