Computer memory power management
A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.
1. A method of using a chip mark in a computer memory system to regulate a computer memory, the method comprising:
detecting a data error in a first memory array of the computer memory system using an error correcting code;
associating, in response to the detecting the data error in the first memory array, the chip mark with the first memory array;
handling the data error in the first memory array;
selecting, in response to receiving a power saving instruction, a non-failing memory array of the computer memory system;
associating, in response to the receiving the power saving instruction, the chip mark with the non-failing memory array; and
placing, in response to the associating the chip mark with the non-failing memory array, the non-failing memory array in a low power mode.
2. The method of claim 1 , wherein:
the handling the data error in the first memory array is by disabling the first memory array.
3. The method of claim 1 , wherein:
the handling the data error in the first memory array uses error correcting code to correct the data error in the first memory array; and further comprising
disassociating, in response to the handling the data error in the first memory array, the chip mark with the first memory array.
4. The method of claim 3 , further comprising:
scrubbing the non-failing memory array before the disassociating the chip mark with the first memory array.
5. The method of claim 1 , wherein the selecting the non-failing memory array is performed by a power switching logic in the computer memory system.
6. The method of claim 1 , wherein the computer memory system receives memory register set data to initiate the transition between the low power mode and a normal power mode.
7. The method of claim 1 , wherein an error correcting code decoder in the computer memory system receives memory register set data to initiate a transition between the low power mode and the normal power mode.
8. The method of claim 1 , wherein the power switching logic provides memory register set data to initiate a transition between the low power mode and the normal power mode.
9. A method of using a chip mark in a computer memory system to regulate a computer memory, the method comprising:
detecting a data error in a first memory array of the computer memory system using an error correcting code;
associating, in response to the detecting the data error in the first memory array, the chip mark with the first memory array;
handling the data error in the first memory array;
selecting, in response to receiving a power saving instruction, a second memory array of the computer memory system; and
associating, in response to the receiving the power saving instruction, the chip mark with an empty location in the second memory array; and
in response to the associating the chip mark with an empty location in the second memory array, instructing the computer memory system to perform less data correction in the second memory array.