Single sided bit line restore for power reduction
A memory circuit to reduce active power is disclosed (FIG. 7 ). The circuit includes a sense amplifier ( 600 ). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit ( 700 ) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.
1. A memory circuit, comprising:
a sense amplifier;
a first bit line coupled to a memory array;
a second bit line coupled to the memory array, wherein the second bit line is arranged as a complementary bit line to the first bit line;
a second transistor having a current path between the sense amplifier and the second bit line; and
a first drive circuit coupled between the sense amplifier and the first bit line and operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.
2. A memory circuit as in claim 1 , wherein the first drive circuit is a transistor having a current path between the sense amplifier and the first bit line.
3. A memory circuit as in claim 1 , wherein the first drive circuit is selected in response to a first row address signal.
4. A memory circuit as in claim 1 , wherein the first drive circuit is a three-state drive circuit.
5. A memory circuit as in claim 1 , wherein the memory array comprises ferroelectric memory cells.
6. A memory circuit as in claim 1 , wherein the memory array comprises one-transistor, one-capacitor (1T1C) memory cells.
7. A memory circuit as in claim 1 , comprising a first transistor having a current path between the sense amplifier and the first bit line.
8. A memory circuit as in claim 7 , wherein the first drive circuit is operable to drive the first data signal from the sense amplifier onto the first bit line when the first transistor is off.
9. A method of operating a memory circuit, comprising:
applying a signal voltage from a memory cell to a first bit line;
applying a reference voltage to a second bit line;
coupling the first and second bit lines to a sense amplifier;
amplifying a difference voltage between the signal voltage and the reference voltage to produce an output voltage by the sense amplifier; and
isolating the second bit line from the sense amplifier while applying the output voltage to the first bit line.
10. A method as in claim 9 , comprising isolating the sense amplifier by forming a high impedance path between the sense amplifier and the second bit line.
11. A method as in claim 9 , comprising isolating the second bit line and applying a predetermined voltage to the second bit line.
12. A method as in claim 11 , wherein the predetermined voltage is 0 V.
13. A method as in claim 9 , wherein the memory cell is one of a ferroelectric memory cell and a dynamic random access memory cell.
14. A method as in claim 9 , wherein the memory cell is one of a one-transistor, one-capacitor (1T1C) memory cell, three-transistor, one-capacitor (3T1C) memory cell, and a four-transistor, one-capacitor (4T1C) memory cell.
15. A method as in claim 9 , comprising isolating the second bit line and floating the second bit line.
16. A method as in claim 9 , comprising applying the output voltage to the first bit line with a three-state drive circuit.
17. A computer system, comprising:
a processor circuit;
an input device coupled to the processor circuit;
an output device coupled to the processor circuit; and
a memory circuit comprising:
a sense amplifier;
a first bit line coupled to a memory array;
a second bit line coupled to the memory array, wherein the second bit line is arranged as a complementary bit line to the first bit line;
a second transistor having a current path between the sense amplifier and the second bit line; and
a first drive circuit coupled between the sense amplifier and the first bit line and operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.
18. A computer system as in claim 17 , wherein the first drive circuit is a transistor having a current path between the sense amplifier and the first bit line.
19. A computer system as in claim 17 , wherein the first drive circuit is operable to drive the first data signal from the sense amplifier onto the first bit line when the first transistor is off.
20. A computer system as in claim 17 , comprising a first transistor having a current path between the sense amplifier and the first bit line.