Semiconductor device and operating method thereof

1. A semiconductor device comprising:

a controller configured to control a first memory device to process a request for the first memory device; and

a second memory device;

wherein the controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk.

2. The semiconductor device of claim 1 , wherein the controller processes the request on the second memory device instead of the first memory device, when data corresponding to the requested address exist in the second memory device.

3. The semiconductor device of claim 1 , wherein the controller updates the information indicating the data damage risk when determining that there is no data damage risk.

4. The semiconductor device of claim 1 , wherein the controller suspends processing the request for the first memory device when there is the data damage risk.

5. The semiconductor device of claim 4 , wherein the controller resumes processing the request for the first memory device after the data is stored in the second memory device.

6. The semiconductor device of claim 1 , further comprising a third memory device configured to store the information indicating the data damage risk.

7. The semiconductor device of claim 1 , wherein the first memory device comprises a volatile memory device.

8. The semiconductor device of claim 7 , wherein the controller resets the information indicating the data damage risk when a refresh operation was performed on the first memory device.

9. The semiconductor device of claim 1 , wherein the information indicating the data damage risk comprises a number of selections for the first signal line.

10. The semiconductor device of claim 9 , wherein when the number of selections for the first signal line exceeds a critical point, the controller determines that there is a data damage risk.

11. The semiconductor device of claim 9 , wherein the controller resets the number of selections for the first signal line when determining that there is the data damage risk.

12. The semiconductor device of claim 9 , wherein the controller updates the number of selections for the first signal line when determining that there is no data damage risk.

13. The semiconductor device of claim 1 , wherein the information indicating the data damage risk comprises a count value for the second signal line.

14. The semiconductor device of claim 13 , wherein when the count value for the second signal line exceeds a critical point, the controller determines that there is a data damage risk.

15. The semiconductor device of claim 13 , wherein the controller resets the count value for the second signal line when determining that there is the data damage risk.

16. The semiconductor device of claim 13 , wherein the controller updates the count value for the second signal line when determining that there is no data damage risk.

17. The semiconductor device of claim 16 , wherein the controller resets the count value for the first signal line when determining that there is no data damage risk.

18. The semiconductor device of claim 1 , wherein the first and second signal lines comprise a word line.