IP Library › Granted Patent US 9,123,613
Granted Patent B2
US 9,123,613 · App. 12/303,567 · Granted Sep 1, 2015

Image sensor and display

Inventors: Christopher James Brown (Lockerbie, GB); Ben James Hadwen (Oxford, GB)
Assignee: Sharp Kabushiki Kaisha
H01L27/14678G06F3/0412H01L27/14632H01L27/14643H04N3/155H04N5/335H04N5/374G02F1/1362G02F1/13338G09G3/3648G09G2360/14
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Quick Facts
Patent No.
US 9,123,613
App. No.
12/303,567
Granted
Sep 1, 2015
Kind
B2
Abstract

An image sensor, for example for incorporation within an active matrix display, comprises an array of sensor elements 10 . Each sensor element ( 10 ) comprise an amplifying transistor (M 1 ) whose gate is connected to an integrating node ( 11 ). The integrating node ( 11 ) is connected to one plate of an integrating capacitor (C 1 ) and to one electrode of a photodiode (D 1 ), whose other electrode is connected to a resetting line (RST). The sensor element ( 10 ) performs a repeating sensing cycle comprising a resetting phase, an integrating phase and a reading phase. During the resetting phase, the resetting line (RST) receives a voltage which forward-biases the photodiode (D 1 ) so as to charge the integrating node ( 11 ) to a predetermined voltage. The resetting line (RST) is then returned to a voltage for reverse-biasing the photodiode (D 1 ) so that the integrating and reading phases may be performed.

Claims (27)

1. An image sensor comprising at least one sensor element, each of the at least one sensor element comprising a semiconductor amplifying element, an integrating capacitor, and a photodiode having a first electrode, which is connected to a first control electrode of the amplifying element and a first terminal of the capacitor, and a second electrode connected to a first control input, which is arranged to receive, during a sensing phase, a first voltage for reverse-biasing the photodiode and to receive, during a resetting phase, a second voltage for forward-biasing the photodiode so as to charge the capacitor to a predetermined voltage.

2. A sensor as claimed in claim 1 , in which the resetting and sensing phases are repeated cyclically.

3. A sensor as claimed in claim 1 , in which the photodiode is a lateral photodiode.

4. A sensor as claimed in claim 1 , in which the photodiode is a thin film diode.

5. A sensor as claimed in claim 1 , in which the amplifying element comprises a voltage-follower arrangement.

6. A sensor as claimed in claim 1 , in which the amplifying element comprises a first transistor.

7. A sensor as claimed in claim 6 , in which the first transistor is a thin film transistor.

8. A sensor as claimed in claim 6 , in which the first transistor is a field effect transistor.

9. A sensor as claimed in claim 5 , in which the first transistor is a field effect transistor, the first transistor is connected as a source-follower and the first control electrode comprises the transistor gate.

10. A sensor as claimed in claim 1 , comprising a semiconductor selection element having a main conductive path connected in series with that of the amplifying element and a second control electrode connected to a second input for controlling selection of the sensor element during a reading phase.

11. A sensor as claimed in claim 10 , in which the selection element comprises a second transistor.

12. A sensor as claimed in claim 11 , in which the second transistor is a thin film transistor.

13. A sensor as claimed in claim 1 , in which the capacitor has a second terminal connected to a second control input, which is arranged to receive, during the sensing phase, a third voltage for disabling the amplifying element and for permitting integration by the capacitor of a photocurrent from the photodiode and to receive, during a reading phase, a fourth voltage for enabling the amplifying element.

14. A sensor as claimed in claim 1 , in which the at least one sensor element comprises a plurality of sensor elements arranged as a first array comprising rows and columns.

15. A sensor as claimed in claim 14 , comprising first row control inputs, each of which is connected to the first control inputs of the sensor elements of a respective row.

16. A sensor as claimed in claim 14 , comprising: a semiconductor selection element having a main conductive path connected in series with that of the amplifying element; a second control electrode connected to a second input for controlling selection of the sensor element during a reading phase; and second row control inputs, each of which is connected to the second control inputs of the sensor elements of a respective row.

17. A sensor as claimed in claim 14 , comprising column outputs, each of which is connected to outputs of the sensor elements of a respective column.

18. A sensor as claimed in claim 17 , in which each column is connected to a respective biasing element.

19. A sensor as claimed in claim 18 , in which each biasing element comprises a third transistor.

20. A sensor as claimed in claim 19 , in which each third transistor is a thin film transistor.

21. A sensor as claimed in claim 14 , comprising an active matrix addressing arrangement for addressing the sensor elements.

22. A display comprising a sensor as claimed in claim 1 and at least one display pixel.

23. A display as claimed in claim 22 , in which the at least one sensor element comprises a plurality of sensor elements arranged as a first array comprising rows and columns, and the at least one pixel comprises a plurality of pixels arranged as a second array comprising a plurality of the rows and a plurality of the columns.

24. A display as claimed in claim 23 , in which each of the sensor elements forms part of at least one pixel.

25. A display as claimed in claim 23 , in which the sensor comprises column outputs, each of which is connected to outputs of the sensor elements of a respective column, the display comprising pixel column data lines, at least two of which connect the column outputs to the sensor elements of the respective columns.

26. A display as claimed in claim 23 , in which the pixels are liquid crystal pixels.

27. A display as claimed in claim 23 , in which the sensor comprises an active matrix addressing arrangement for addressing the sensor elements, the active matrix addressing arrangement is being arranged to address each row of sensor elements during a line blanking period of a corresponding row of pixels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2008
From: BROWN, CHRISTOPHER JAMES; HADWEN, BEN JAMES
To: SHARP KABUSHIKI KAISHA
Reel/Frame 021934/0722 →
Priority Claims (1)
GB 0611537.2 · Jun 12, 2006 · national
Continuity (1)
Related Publication 20100238135A1 · Sep 23, 2010