Memory process and memory structure made thereby
A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
1. A memory structure, comprising:
a substrate, having therein a plurality of trenches, and having thereon an array area and a contact area apart from the array area, wherein each trench has a first portion in the contact area and a second portion in the array area, and the substrate between the first portions of the trenches is also in the contact area and has a surface lower than a surface of the substrate between the trenches outside of the contact area;
a plurality of conductive lines, each buried in a trench and having an array portion in the array area and a contact portion in the contact area, wherein the contact portion is protruding above the lower surface of the substrate between the first portions of the trenches in the contact area; and
an insulating layer, filling in gaps between protruding parts of the contact portions of the conductive lines in the contact area.
2. The memory structure of claim 1 , further comprising, on the contact portion of each of the conductive lines, at least one contact plug.
3. The memory structure of claim 1 , further comprising a substantially conformal protective layer covering the contact portions of the conductive lines.
4. The memory structure of claim 3 , further comprising, on the contact portion of each of the conductive lines and through the protective layer, at least one contact plug.
5. The memory structure of claim 1 , wherein the insulating layer comprises a spin-on dielectric (SOD) layer.
6. The memory structure of claim 1 , wherein the conductive lines are word lines of a DRAM.
7. The memory structure of claim 1 , wherein a width of the contact area ranges from 500 nm to 550 nm.
8. The memory structure of claim 1 , wherein in the contact area, the surface of the substrate is lower than the tops of the contact portions of the conductive lines by 7.5-10 nm.