IP Library Granted Patent US 9,130,013
Granted Patent B2
US 9,130,013 · App. 13/941,964 · Granted Sep 8, 2015

Semiconductor device and method of manufacturing the same

Inventors: Seung Cheol Lee (Icheon-si, KR); Yang Bok Lee (Seoul, KR)
Assignee: SK Hynix Inc.
H01L21/76224H01L21/764H01L27/11519H01L27/11524H01L29/66825
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Quick Facts
Patent No.
US 9,130,013
App. No.
13/941,964
Granted
Sep 8, 2015
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines.

Claims (12)

1. A semiconductor device, comprising:

trenches formed in a first direction in parallel at isolation regions of a semiconductor substrate;

first air gaps formed in the trenches;

gate lines formed in a second direction crossing the first direction over the first air gaps and active regions of the semiconductor substrate between the isolation regions;

an interlayer insulating layer formed over the semiconductor substrate including the gate lines; and

second air gaps formed between the gate lines in the interlayer insulating layer,

wherein the gate lines comprise select gate lines and cell gate lines between the select gate lines, and the first air gaps in the trenches are isolated below the select gate lines.

2. The semiconductor device of claim 1 , further comprising isolation layers in the trenches below the first air gaps.

3. The semiconductor device of claim 2 , wherein the isolation layers comprise a polysilazane (PSZ) material.

4. The semiconductor device of claim 2 , wherein the isolation layer below the gate line is higher than the isolation layer between the gate lines.

5. The semiconductor device of claim 1 , wherein the cell gate lines have a narrower width than the select gate lines.

6. The semiconductor device of claim 1 , wherein the first air gaps are oval-shaped having upper portions wider than lower portions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: LEE, SEUNG CHEOL; LEE, YANG BOK
To: SK HYNIX INC.
Reel/Frame 030801/0426 →
Priority Claims (1)
KR 10-2013-0023386 · Mar 5, 2013 · national
Continuity (1)
Related Publication 20140252434A1 · Sep 11, 2014