Array substrate, liquid crystal panel and liquid crystal display device
View Patent ↗Embodiments of the invention provide an array substrate, a liquid crystal display panel and a liquid crystal display device. The array substrate comprises a plurality of array substrate units, each of which comprising: gate lines and data lines extending along a first direction and a second direction crossing with each other, respectively, in a plane of a substrate. Each array substrate unit comprises four array substrate sub-units which are arranged in the first direction and the second direction to form sub-unit rows and sub-unit columns, and each of sub-unit rows and sub-unit columns has two array substrate sub-units. The three gate lines are shared by two array substrate sub-units in each sub-unit row, and the one data line and one of the gate lines are shared by two array substrate sub-units in each sub-unit column.
1. An array substrate, comprising a plurality of array substrate units, each of which comprising:
gate lines and data lines extending along a first direction and a second direction crossing with each other, respectively, in a plane of a substrate, wherein,
each array substrate unit comprises four array substrate sub-units which are arranged in the first direction and the second direction to form sub-unit rows and sub-unit columns, and each of sub-unit rows and sub-unit columns has two array substrate sub-units,
each array substrate sub-unit comprises three pixels, and one data line and three gate lines which are electrically connected to the three pixels, the three gate lines comprising a first gate line, a second gate line and a third gate line; and the three gate lines are shared by two array substrate sub-units in each sub-unit row, and the one data line and one of the gate lines are shared by two array substrate sub-units in each sub-unit column, and wherein,
within each array substrate sub-unit, the first gate line, the three pixels, the second gate line and the third gate line are arranged sequentially in the second direction; within each array substrate unit, the first sub-unit row and the second sub-unit row are arranged sequentially in the second direction, the third gate line for the first sub-unit row and the first gate line for the second sub-unit row are the same gate line.
2. The array substrate according to claim 1 , wherein, within each array substrate sub-unit, the three pixels are arranged in the first direction.
3. The array substrate according to claim 1 , wherein, within each array substrate sub-unit, each pixel is electrically connected to a corresponding gate line and a corresponding data line, respectively, through a switch.
4. The array substrate according to claim 3 , wherein the switch is a thin-film transistor (TFT).
5. The array substrate according to claim 4 , wherein the three pixels are a first pixel, a second pixel and a third pixel, respectively; and within each array substrate sub-unit, the first pixel is electrically connected to the first gate line, the third gate line and the data line through a first TFT and a second TFT, respectively, a gate electrode of the first TFT is connected to the third gate line, a drain electrode of the first TFT is connected to the first gate line, a source electrode of the first TFT is connected to a gate electrode of the second TFT, a drain electrode of the second TFT is connected to the data line, a source electrode of the second TFT is connected to the first pixel; the second pixel is electrically connected to the second gate line, the third gate line and the data line through a third TFT and a fourth TFT, respectively, a gate electrode of the third TFT is connected to the third gate line, a drain electrode of the third TFT is connected to the second gate line, a source electrode of the third TFT is connected to a gate electrode of the fourth TFT, a drain electrode of the fourth TFT is connected to the data line, a source electrode of the fourth TFT is connected to the second pixel; the third pixel is electrically connected to the first gate line and the data line through a fifth TFT, a gate electrode of the fifth TFT is connected to the first gate line, a drain electrode of the fifth TFT is connected to the data line, and a source electrode of the fifth TFT is connected to the third pixel.
6. The array substrate according to claim 1 , wherein a plurality of the array substrate units are arranged in a matrix, and in the second direction, the last third gate line in a previous array substrate unit and the foremost first gate line in a next array substrate unit are the same gate line.
7. The array substrate according to claim 1 , wherein the first direction and the second direction are perpendicular to each other.
8. The array substrate according to claim 1 , wherein the gate lines are configured to supply driving signals, and the data line is configured to supply voltage signals polarities of which are reversed continuously.
9. A liquid crystal display panel, comprising a color filter substrate, an array substrate and liquid crystal interposed between the color filter substrate and the array substrate, wherein the array substrate is an array substrate according to claim 1 .
10. A liquid crystal display device, comprising a backlight, a liquid crystal panel, and an integrated circuit board that provides control signals to the liquid crystal panel, the liquid crystal display panel comprising a color filter substrate, an array substrate and liquid crystal interposed between the color filter substrate and the array substrate, wherein the array substrate is an array substrate according to claim 1 .