Temperature based logic profile for variable resistance memory cells

1. An apparatus comprising at least one variable resistance memory cell having a logic state corresponding to a first range of resistance values replaced with a second range of resistance values by a controller, the second range of resistance values selected in response to a predicted resistance shift based upon a logic profile.

2. The apparatus of claim 1 , wherein the at least one variable resistance memory cell is individually programmable, non-flash memory.

3. The apparatus of claim 1 , wherein the at least one variable resistance memory cell is part of a solid-state memory array.

4. The apparatus of claim 3 , wherein the solid-state memory array has a plurality of different types of variable resistance memory cells.

5. The apparatus of claim 4 , wherein a first type of variable resistance memory cell comprises a programmable metallization cell.

6. The apparatus of claim 5 , wherein a second type of variable resistance memory cell comprises a phase change random access memory cell.

7. The apparatus of claim 6 , wherein a third type of variable resistance memory cell comprises a resistive random access memory cell.

8. The apparatus of claim 1 , wherein the controller comprises an evaluation engine configured to concurrently analyze a plurality of different memory cell operational conditions to reactively identify resistance variance in the at least one variable resistance memory cell.

9. The apparatus of claim 8 , wherein the evaluation engine provides a model generator with data to proactively predict resistance variance in the at least one variable resistance memory cell.

10. The apparatus of claim 1 , wherein the second range of resistance values corrects for the predicted resistance shift.

11. A method comprising predicting resistance shift with a logic profile for at least one variable resistance memory cell, and replacing a first range of resistance values corresponding to a logic state with a second logic range of resistance values by a controller based upon the predicted resistance shift of the logic profile.

12. The method of claim 11 wherein the logic profile predicts bit error rate and resistance variation for a plurality of different operating temperatures.

13. The method of claim 11 , wherein the predicted resistance shift corresponds to predicted resistance variation with measured operational temperature.

14. The method of claim 11 , wherein the logic profile indicates when to adjust the at least one variable resistance memory cell to the second range of resistance values to maintain a bit error rate below a predetermined reliability threshold.

15. The method of claim 11 , wherein the at least one variable resistance memory cell is transitioned from a multi-bit cell to a single bit cell in response to the predicted resistance shift.

16. The method of claim 11 , wherein the at least one variable resistance memory cell is operated at temperatures above manufacturer's specifications.

17. The method of claim 11 , wherein a plurality of variable resistance memory cells are concurrently set to the second range of resistance values in response to the predicted resistance shift.

18. The method of claim 11 , wherein a single variable resistance memory cell is set to the second range of resistance values in response to the predicted resistance shift.

19. A data storage device comprising:

a controller;

a logic profile engine; and

at least one variable resistance memory cell having a first range of resistance values replaced with a second range of resistance values by the controller in response to the first range of resistance values corresponding to a predicted resistance shift in a logic profile generated by the logic profile engine.

20. The data storage device of claim 19 , wherein the logic profile engine predicts when the at least one variable resistance memory cell will exceed a reliability threshold corresponding with a predetermined bit error rate.