Thermally enhanced structure for multi-chip device
A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
1. A method comprising:
attaching a heat sink block to a first side of a first semiconductor die, wherein a length of the heat sink block is equal to a length of the first semiconductor die;
bonding a second side of the first semiconductor die to an interposer; and
bonding the interposer to a substrate, wherein the first semiconductor die is located between the interposer and the substrate.
2. The method of claim 1 , wherein:
the heat sink block is attached to a backside surface of the first semiconductor die; and
the heat sink block has a plurality of openings.
3. The method of claim 1 , further comprising:
placing one additional heat sink between the heat sink block and the top surface of the substrate.
4. The method of claim 1 , further comprising:
coupling the first semiconductor die to the interposer through a plurality of micro bumps placed between the first semiconductor die and the interposer.
5. The method of claim 1 , further comprising:
coupling the interposer to the substrate through a plurality of solder balls placed between the substrate and the interposer.
6. The method of claim 1 , further comprising:
forming a solder joint structure between the heat sink block and the top surface of the substrate.
7. The method of claim 1 , wherein:
the heat sink block has a first side attached to the first side of the first semiconductor die; and
the heat sink block has a second side in direct contact with a top surface of the substrate.
8. A method comprising:
attaching a first surface of a first semiconductor die to a first surface of a second semiconductor die;
attaching a heat sink to a second surface of the first semiconductor die;
forming an encapsulation material layer on the first semiconductor die and the second semiconductor die;
forming a plurality of via openings in the encapsulation material layer;
filling a conductive material into the via openings;
forming a redistribution layer on the encapsulation material layer;
forming a plurality of under bump metallization structures on the redistribution layer; and
forming a plurality of solder balls on the plurality of under bump metallization structures.
9. The method of claim 8 , further comprising:
forming a third semiconductor die;
attaching the third semiconductor die to the first semiconductor die via a plurality of micro bumps;
extending the heat sink such that a side of the heat sink opposite the first semiconductor die touches a first surface of the redistribution layer; and
forming a solder ball attached to a surface of the second redistribution layer.
10. The method of claim 8 , further comprising:
forming a variety of thermal openings in the heat sink; and
forming a variety of thermal vias in the heat sink.
11. A method comprising:
providing a first chip with a first redistribution layer;
attaching a first side of a second chip to the first chip;
forming a heat sink on a second side of the second chip;
forming an encapsulation layer over the first chip, wherein the second chip is embedded in the encapsulation layer; and
forming a plurality of vias in the encapsulation layer.
12. The method of claim 11 , further comprising:
attaching the first side of the second chip to the first chip through an epoxy layer.
13. The method of claim 11 , further comprising:
forming a face-to-face connection between the first chip and the second chip, wherein a plurality of micro bumps are formed between the first chip and the second chip.
14. The method of claim 11 , further comprising:
forming first openings extending from a top surface of the encapsulation layer to a top surface of the first chip; and
forming second openings extending from the top surface of the encapsulation layer to a top surface of the second chip.
15. The method of claim 14 , further comprising:
filling the first openings with a conductive material to form first vias; and
filling the second openings with the conductive material to form second vias.
16. The method of claim 11 , wherein:
the heat sink has a plurality of openings.
17. The method of claim 11 , further comprising:
forming a second redistribution layer over a top surface of the encapsulation layer.
18. The method of claim 17 , further comprising:
forming a plurality of under bump metallization (UBM) structures over the second redistribution layer.