3D semiconductor device and structure with back-bias
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
1. A 3D semiconductor device, comprising:
a first layer comprising first transistors;
a first interconnection layer interconnecting said first transistors and comprises aluminum or copper;
a second layer comprising second transistors; and
at least one through-layer via;
wherein said at least one through-layer via comprises a conductive path through said second layer,
wherein said at least one through-layer via has a diameter less than 200 nm,
wherein said second layer comprises at least one Flip-Flop,
wherein said second layer is overlying said first interconnection layer, and
wherein at least one of said second transistors has a back-bias structure designed to modify the performance of said at least one of said second transistors, wherein said second transistors comprise mono-crystalline material.
2. A 3D semiconductor device according to claim 1 ,
wherein the interconnection layer is between said first layer and said second layer;
wherein said second transistors are horizontally oriented transistors.
3. A 3D semiconductor device according to claim 1 ,
wherein said second transistors comprise a source contact, said source contact comprising a silicide, and
wherein said silicide has a sheet resistance of less than 15 ohm/sq.
4. A 3D semiconductor device according to claim 1 ,
wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.
5. A 3D semiconductor device according to claim 1 ,
wherein the interconnection layer is between said first layer and said second layer;
wherein said second transistors comprise mono-crystalline material,
wherein said second transistors are horizontally oriented transistors, and
wherein said second transistors are Fin-FET transistors.
6. A 3D semiconductor device according to claim 1 , wherein said second transistors are fully depleted transistors.
7. A 3D semiconductor device according to claim 1 , further comprising:
a heat spreader layer disposed between said first layer and said second layer.
8. A 3D semiconductor device, comprising:
a first layer comprising first transistors;
a first interconnection layer interconnecting said first transistors and comprises aluminum or copper;
a second layer comprising second transistors; and
at least one through-layer via;
wherein said at least one through-layer via comprises a conductive path through said second layer,
wherein said at least one through-layer via has a diameter less than 200 nm,
wherein said second layer is overlying said first interconnection layer,
wherein at least one of said second transistors has a back-bias structure, wherein said second transistors comprise mono-crystalline material.
9. A 3D semiconductor device according to claim 8 ,
wherein the interconnection layer is between said first layer and said second layer;
wherein said second transistors are horizontally oriented transistors.
10. A 3D semiconductor device according to claim 8 ,
wherein said second transistors comprise a source contact, said source contact comprising a silicide, and
wherein said silicide has a sheet resistance of less than 15 ohm/sq.
11. A 3D semiconductor device according to claim 8 ,
wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.
12. A 3D semiconductor device according to claim 8 , further comprising:
a heat spreader layer disposed between said second layer and said interconnection layer,
wherein the interconnection layer is between said first layer and said second layer.
13. A 3D semiconductor device according to claim 8 , wherein said second transistors are fully depleted transistors.
14. A 3D semiconductor device according to claim 8 ,
wherein at least two of said second transistors have a common shared diffusion.
15. A 3D semiconductor device, comprising:
a first layer comprising first transistors;
a second layer comprising second transistors;
wherein said second layer is overlying said first transistors,
wherein said second transistors comprise a first mono-crystalline material,
wherein at least one of said second transistors has a back-bias structure,
at least one through-layer via;
wherein said at least one through-layer via comprises a conductive path through said second layer,
wherein said at least one through-layer via has a diameter less than 200 nm, and
an interconnection layer between said first layer and said second layer,
wherein said interconnection layer comprises copper or aluminum,
wherein said second layer comprises a plurality of Flip-Flops, and
wherein said plurality of Flip-Flops comprise scanned Flip-Flops connected with a scan chain.
16. A 3D semiconductor device according to claim 15 ,
wherein said second transistors are horizontally oriented transistors.
17. A 3D semiconductor device according to claim 15 ,
wherein said second transistors comprise a source contact, said source contact comprising a silicide, and
wherein said silicide has a sheet resistance of less than 15 ohm/sq.
18. A 3D semiconductor device according to claim 15 ,
wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.
19. A 3D semiconductor device according to claim 15 ,
wherein said second transistors are fully depleted transistors.
20. A 3D semiconductor device according to claim 15 , further comprising:
a heat spreader layer disposed between said first layer and said second layer.