Compliant printed circuit wafer level semiconductor package
A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.
1. A method of making a wafer-level semiconductor package, the method comprising the step of:
printing at least one dielectric layer selectively on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices;
depositing a conductive material in a plurality of the first recesses to form contact members on the semiconductor devices;
printing at least one dielectric layer selectively on at least a portion of the wafer to create a plurality of second recesses corresponding to a target circuit geometry;
depositing a conductive material in at least a portion of the second recesses to form a circuit geometry, the circuit geometry comprising a plurality of exposed terminals electrically coupled to the plurality of packaged semiconductor devices on the wafer; and
dicing the wafer having the plurality of packaged semiconductor devices into a plurality of discrete packaged semiconductor devices.
2. The method of claim 1 comprising plating with a conductive material one or more of the contact members and the circuit geometry.
3. The method of claim 1 comprising depositing a compliant material in a location between the semiconductor devices and at least one of the exposed terminals.
4. The method of claim 1 comprising:
printing at least one electrical device on a dielectric layer; and
electrically coupling the electrical device to at least a portion of the circuit geometry.
5. The method of claim 1 comprising forming at least one via in a dielectric layer to electrically couple adjacent layers of the circuit geometry.
6. The method of claim 1 comprising forming one or more contact members on the exposed terminals that extend above the dielectric layer.
7. The method of claim 1 comprising the steps of:
locating a plurality of semiconductor devices on the discrete packaged semiconductor device; and
forming the circuit geometry to include at least one of an inter-die circuit path or an intra-die circuit paths.
8. The method of claim 1 comprising the steps of:
vertically stacking at least two semiconductor devices in the discrete packaged semiconductor devices; and
electrically coupling at least two of the stacked semiconductor devices with through silicon vias.
9. The method of claim 1 comprising electrically coupling a second semiconductor device to the exposed terminals on the discrete packaged semiconductor devices.
10. The method of claim 1 wherein conductive traces in the circuit geometry comprise substantially rectangular cross-sectional shapes.
11. The method of claim 1 comprising depositing a conductive material, a non-conductive material, and a semi-conductive material on a single layer.
12. The method of claim 1 comprising the steps of:
locating pre-formed conductive trace materials in the second recesses; and
plating the second recesses to form conductive traces with substantially rectangular cross-sectional shapes.
13. The method of claim 1 comprising the steps of:
pressing a conductive foil into at least a portion of the second recesses;
shearing the conductive foil along edges of the second recesses;
removing excess conductive foil not located in the second recesses; and
plating the second recesses to form conductive traces with substantially rectangular cross-sectional shapes.
14. A method of making an electrical assembly comprising the steps of:
making the discrete packaged semiconductor device according to the method of claim 1 ; and
electrically coupling a circuit member with a plurality of the exposed terminals on the discrete packaged semiconductor devices.
15. The method of claim 14 wherein the circuit member is selected from one of a dielectric layer, a printed circuit board, a flexible circuit, a bare die device, an integrated circuit device, organic or inorganic substrates, or a rigid circuit.
16. A method of making a wafer-level semiconductor package, the method comprising the step of:
printing at least one dielectric layer selectively on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices;
depositing a conductive material in a plurality of the first recesses to form contact members on the semiconductor devices;
printing at least one dielectric layer selectively on at least a portion of the wafer to create a plurality of second recesses corresponding to a target circuit geometry;
depositing a conductive material in at least a portion of the second recesses to form a circuit geometry, the circuit geometry comprising a plurality of exposed terminals electrically coupled to the semiconductor devices on the wafer; and
dicing the wafer into a plurality of discrete packaged semiconductor devices after the step of depositing the conductive material in the second recesses.