Semiconductor device

1. A semiconductor device, comprising:

a channel layer;

insulating layers surrounding the channel layer and stacked along the channel layer;

first grooves and second grooves alternately disposed on regions between the insulating layers, wherein the first grooves and the second grooves have different widths; and

a first conductive layer in each of the first grooves,

wherein the insulating layers are separated from each other by the first and second grooves.

2. The semiconductor device of claim 1 , further comprising a plurality of data storage patterns surrounding the channel layer and separated from each other by the second grooves.

3. The semiconductor device of claim 2 , further comprising first charge blocking layers formed on surfaces of the data storage patterns.

4. The semiconductor device of claim 1 , further comprising second charge blocking layers formed on surfaces of the first and second grooves.

5. The semiconductor device of claim 1 , further comprising a barrier layer formed in each of the second grooves.

6. The semiconductor device of claim 1 , further comprising an air gap formed in each of the second grooves.

7. The semiconductor device of claim 2 , further comprising spacers formed on sidewalls of the data storage patterns.

8. The semiconductor device of claim 1 , wherein each of the second grooves has a smaller width than each of the first grooves.

9. A semiconductor device, comprising:

at least one channel layer;

insulating layers stacked while surrounding the at least one channel layer;

first grooves and second grooves alternately interposed between the insulating layers;

conductive layers formed in the first grooves; and

data storage patterns surrounding the channel layers and separated from each other by the second grooves, wherein each of the data storage patterns extends along sidewalls of one of the conductive layers and two of the insulating layers located between adjacent second grooves.

10. The semiconductor device of claim 9 , further comprising barrier layers formed in the second grooves.

11. The semiconductor device of claim 9 , further comprising air gaps formed in the second grooves.

12. The semiconductor device of claim 9 , further comprising spacers formed on sidewalls of the data storage patterns.

13. The semiconductor device of claim 9 , further comprising first charge blocking layers formed on surfaces of the data storage patterns exposed through the first grooves.

14. The semiconductor device of claim 9 , further comprising second charge blocking layers formed on surfaces of the first and second grooves.

15. The semiconductor device of claim 9 , wherein each of the second grooves has a smaller width than each of the first grooves.

16. A semiconductor device, comprising:

at least one channel layer;

insulating layers stacked while surrounding the at least one channel layer;

first grooves interposed between the insulating layers;

second grooves interposed between the first grooves and the insulating layers, wherein the second grooves are located above and below each of the first grooves to meet the first grooves;

data storage patterns surrounding the channel layers and separated from each other by the second grooves; and

conductive layers formed in the first and second grooves.

17. The semiconductor device of claim 16 , further comprising first charge blocking layers formed on surfaces of the data storage patterns.

18. The semiconductor device of claim 16 , further comprising second charge blocking layers formed on surfaces of the first and second grooves.

19. The semiconductor device of claim 16 , wherein each of the second grooves has a smaller width than each of the first grooves.

20. The semiconductor device of claim 16 , wherein the conductive layers surround surfaces of the data storage patterns.