Memory structures and arrays
Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.
1. A memory structure, comprising:
a memory cell having programmable material between a pair of electrodes; the programmable material comprising a multivalent metal oxide directly against a high-k dielectric; and
a diode over the memory cell; the diode comprising a first diode electrode directly over one of the memory cell electrodes and electrically coupled with said one of the memory cell electrodes; the diode further comprising a second diode electrode laterally outward of the first diode electrode; the entirety of the second diode electrode not being directly over the memory cell.
2. The memory structure of claim 1 wherein the high-k dielectric comprises an oxide which includes one or more of hafnium, zirconium, yttrium, and aluminum.
3. The memory structure of claim 1 wherein the multivalent metal oxide comprises one or more of barium, ruthenium, strontium, titanium, calcium, manganese, praseodymium, lanthanum and samarium.
4. The memory structure of claim 1 wherein the multivalent metal oxide comprises calcium manganese oxide doped with one or more of Pr, La, Sr and Sm.
5. The memory structure of claim 1 further comprising an intermediate diode region between the first and second diode electrodes.
6. The memory structure of claim 5 wherein the intermediate diode region is not directly over the memory cell.
7. The memory structure of claim 5 wherein the second diode electrode is comprised of a pair of second diode electrode segments that are on opposing sides of the first diode electrode relative to one another.
8. The memory structure of claim 5 wherein the first and second diode electrodes comprise metal.
9. The memory structure of claim 5 wherein at least one of the first and second diode electrodes comprises titanium nitride, and wherein the intermediate diode region comprises silicon.
10. The memory structure of claim 9 wherein the intermediate diode region comprises at least one p-type doped domain and at least one n-type doped domain.
11. A memory structure, comprising:
a memory cell comprising programmable material between a pair of electrodes; the programmable material comprising a multivalent metal oxide directly against a high-k dielectric;
a first diode electrode directly over and directly against one of the memory cell electrodes;
a pair of intermediate diode region segments on opposing sides of the first diode electrode;
a pair of second diode electrode segments on opposing sides of the first diode electrode and laterally outward of the intermediate diode region segments; and
the entireties of the second diode electrode segments and the intermediate diode region segments not being directly over the memory cell.
12. The memory structure of claim 11 wherein the intermediate diode region segments extend to under the second diode electrodes.
13. The memory structure of claim 11 wherein the first diode electrode and the second diode electrode segments are compositionally the same as one another, and wherein the intermediate diode region segments comprise at least two different domains.
14. A memory array, comprising:
a first series of access/sense lines; the lines of the first series extending primarily along a first direction;
a second series of access/sense lines over the first series; the lines of the second series extending primarily along a second direction that intersects the first direction;
a plurality of memory structures between the first and second series of access/sense lines, with individual memory structures being at regions where the second series of access/sense lines overlap the first series of access/sense lines; at least some of the individual memory structures comprising:
a memory cell comprising programmable material between a pair of electrodes; the programmable material comprising a multivalent metal oxide directly against a high-k dielectric; and
a diode over the memory cell; the diode comprising a first diode electrode directly over one of the memory cell electrodes and electrically coupled with said one of the memory cell electrodes; the diode further comprising a second diode electrode, and an intermediate diode region between the first and second diode electrodes; the second diode electrode being laterally outward of the first diode electrode, with an entirety of the second diode electrode Not being directly over the memory cell; and
wherein the access/sense lines of the second series are directly electrically coupled with the second diode electrodes and are not directly electrically coupled with the first diode electrodes.
15. The memory array of claim 14 wherein the second diode electrode is comprised of a pair second diode electrode segments that are on opposing sides of the first diode electrode relative to one another.
16. The memory array of claim 15 wherein the first and second diode electrodes comprise metal.
17. The memory array of claim 16 wherein at least one of the first and second diode electrodes comprises titanium nitride, and wherein the intermediate diode region comprises semiconductor material.
18. The memory array of claim 17 wherein the first and second diode electrodes both comprise titanium nitride, and wherein the intermediate diode region comprise at least one p-type doped domain and at least one n-type doped domain.