IP Library Granted Patent US 9,136,307
Granted Patent B2
US 9,136,307 · App. 13/369,654 · Granted Sep 15, 2015

Memory cells and memory cell formation methods using sealing material

Inventor: Fabio Pellizzer (Cornate d'Adda, IT)
Assignee: Micron Technology, Inc.
H01L27/2427H01L27/2481H01L45/06H01L45/1233H01L45/144H01L45/1675
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Quick Facts
Patent No.
US 9,136,307
App. No.
13/369,654
Granted
Sep 15, 2015
Kind
B2
Abstract

Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.

Claims (56)

1. A method of forming a memory cell, comprising:

forming a stack of materials on a conductive material, the stack of materials comprising:

an active storage element material in direct contact with and between a first electrode material and a second electrode material;

an active select device material in direct contact with and between the second electrode material and a third electrode material; and

the conductive material associated with a conductive line corresponding to the memory cell;

forming a trench to a first depth that ends on the second electrode material in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench;

forming a sealing material on the exposed portion of the at least one of the active storage element material and the active select device material and on an exposed portion of the second electrode material such that at least a portion of the sealing material is exposed on the sidewalls of the trench; and

deepening the trench through a remaining portion of the stack, including the conductive material, such that a portion of the other of the at least one of the active storage element material and the active select device material is the portion that is exposed first on the sidewalls of the trench, other than previously exposed materials, after initiation of the deepening.

2. The method of claim 1 , further comprising passivating the sidewalls with the sealing material formed thereon from subsequent contamination during cleaning of the trench after forming the trench and before, during, and after deepening of the trench.

3. The method of claim 2 , wherein passivating the sidewalls with the sealing material formed thereon includes passivating the portion of the at least one of the active storage element material and the active select device material with the sealing material formed thereon from subsequent contamination during cleaning of the trench after forming the trench and before, during, and after deepening of the trench.

4. The method of claim 1 , wherein deepening the trench includes etching the trench through the other of the at least one of the active storage element material and the active select device material and the conductive material.

5. The method of claim 1 , wherein forming the sealing material includes depositing the sealing material with atomic layer deposition (ALD) to a thickness of not greater than about 5 nanometers.

6. The method of claim 1 , further comprising forming a sealing material on the exposed portion of the other of the at least one of the active storage element material and the active select device material prior to subsequent etching in order to passivate the formerly exposed portion of the of the other of the at least one of the active storage element material and the active select device material during the subsequent etching.

7. A method of forming a plurality of memory cells, comprising:

forming a first stack of materials on a first conductive material, wherein forming the first stack comprises:

forming an active select device material in direct contact with and between a first electrode material and a second electrode material and forming an active resistive storage element material in direct contact with and between the second electrode material and a third electrode material;

forming first trenches in the first stack by etching through the first stack in a first direction, wherein forming the first trenches comprises:

performing an initial etch through a first portion of the first stack to form a plurality of initial trenches in the first direction;

forming a sealing material on sidewalls of the plurality of initial trenches such that at least a portion of the sealing material is exposed; and

performing a second etch through a remaining portion of the first stack and the first conductive material, wherein:

the initial etch exposes at least a portion of the second electrode material and only one of:

a portion of the active select device material; and

a portion of the active resistive storage element material;

the second etch exposes an other of the portion of the active resistive storage element material and the portion of the active select device material that was not exposed in the initial etch; and

the other of the portion of the active resistive storage element material and the portion of the active select device material is the portion that is exposed first, other than previously exposed materials, during the second etch.

8. The method of claim 7 , further comprising:

forming a second stack of materials on the first stack;

forming second trenches by etching through the second stack and at least a first portion of the first stack in a second direction, wherein forming the second trenches comprises:

performing an initial etch through the second stack and the at least a first portion of the first stack to form a plurality of initial trenches in the second direction;

forming a sealing material on sidewalls of the plurality of initial trenches in the second direction; and

performing an additional etch through at least a second portion of the first stack.

9. The method of claim 7 , wherein performing the second etch through the first conductive material includes forming first conductive lines corresponding to the memory cells.

10. The method of claim 8 , wherein performing the additional etch through the at least the second portion of the first stack includes ending the additional etch on the first conductive material corresponding to the first conductive lines.

11. The method of claim 7 , wherein the active select device material, the first electrode material, and the second electrode material corresponds to an ovonic threshold switch (OTS), and wherein the active resistive storage element material, the second electrode material and the third electrode material correspond to a phase change storage element.

12. The method of claim 7 , further comprising forming the first electrode material in direct contact with the first conductive material.

13. The method of claim 12 , wherein forming the sealing material on the sidewalls of the initial trenches includes sealing at least a portion of the active resistive storage element material.

14. The method of claim 7 , further comprising forming the third electrode material in direct contact with the first conductive material.

15. The method of claim 14 , wherein forming the sealing material on the sidewalls of the initial trenches includes sealing at least a portion of the active select device material.

16. The method of claim 7 , wherein forming the first stack of materials includes forming an active select device material between a first electrode material and a second electrode material, forming an active resistive storage element material between the second electrode material and a third electrode material, and forming a second conductive material on the third electrode material.

17. The method of claim 15 , wherein the second stack of materials includes a second conductive material and wherein performing the initial etch through the second stack and the at least the first portion of the first stack includes etching through the second conductive material to form second conductive lines.

18. The method of claim 7 , wherein forming the first trenches further comprises performing an etch through a second portion of the first stack such that a depth of the first plurality of initial trenches is increased subsequent to forming the sealing material on the sidewalls of the plurality of initial trenches and prior to performing the second etch.

19. The method of claim 18 , further comprising forming a sealing material on the sidewalls of the plurality of initial trenches to the increased depth.

20. The method of claim 19 , wherein forming the sealing material on the sidewalls of the plurality of initial trenches to the increased depth includes sealing at least a portion of the at least one of the active resistive storage element material and the active select device material.

21. A method of forming a plurality of memory cells, comprising:

forming a first stack of materials on a substrate, wherein the first stack comprises;

a first electrode material;

an active resistive storage element material in series with an active select device material, wherein a second electrode material is formed in direct contact with and between the active resistive storage element material and the active select device material;

a third electrode material on an opposite side of the stack from the first electrode;

forming a first initial trench in a first direction through the third electrode material and ending in the second electrode material such that at least a portion of the second electrode material is exposed;

forming a first sealing material on sidewalls of the first initial trench such that at least a portion of a surface of the first sealing material is exposed; and

continuing forming the first initial trench in the first direction by etching through the first sealing material on a bottom of the first initial trench and a remaining portion of the second electrode material such that a portion of at least one of the active resistive storage element material and the active select device material is the portion that is exposed first, other than previously exposed materials, during the etching.

22. The method of claim 21 , further comprising forming a first completed trench in the first direction by etching through: the first electrode material; a remaining portion of the at least one of the active resistive storage element material and the active select device material; and a first conductive material associated with a remaining portion of the first stack.

23. The method of claim 22 , further comprising forming a second stack of materials on the third electrode material, the second stack comprising a second conductive material that covers the first completed trench and is in direct contact with the first sealing material and a first dielectric material formed therein.

24. The method of claim 23 , further comprising forming a second initial trench in a second direction by etching through: a second hard mask material of the second stack; the second conductive material of the second stack; the third electrode material; and wherein the second initial trench ends on the second electrode material.

25. The method of claim 24 , further comprising forming a second sealing material on the second hard mask material remaining on the second conductive material and sidewalls of the second initial trench to a depth of the second initial trench.

26. The method of claim 25 , further comprising forming a second completed trench in the second direction by etching through: second sealing material formed on a bottom of the second initial trench; the second electrode material; the first electrode material; and wherein the completed etch ends on the first conductive material.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2012
From: PELLIZZER, FABIO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027679/0202 →
Continuity (1)
Related Publication 20130207068A1 · Aug 15, 2013