Array substrate, display panel, display device and method for driving array substrate

1. An array substrate comprising: gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode; and the array substrate further comprises compensation capacitors on the array substrate;

in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs; and

in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and another end electrically connected to a gate line in a next row.

2. The array substrate according to claim 1 , wherein in every two adjacent rows of gate lines in all the rows on the array substrate, the first type of pixel TFTs connected with one gate line are N-type TFTs, and the second type of pixel TFTs connected with the other gate line are P-type TFTs; and

in all the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and the other end electrically connected to a gate line in a next row.

3. The array substrate according to claim 1 , wherein in the pixel TFTs electrically connected with a gate line, a capacitance of a compensation capacitor connected with a pixel TFT at a shorter distance from a starting end of the gate line is greater than a capacitance of a compensation capacitor connected with a pixel TFT at a longer distance from the starting end of the gate line.

4. A display panel, comprising an array substrate, wherein the array substrate comprises: gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode; and the array substrate further comprises compensation capacitors on the array substrate;

in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs; and

in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and an other end electrically connected to a gate line in a next row.

5. A method for driving an array substrate, wherein the array substrate comprises gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode; and the array substrate further comprises compensation capacitors on the array substrate;

in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs; and in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and an other end electrically connected to a gate line in a next row,

and wherein the method comprises:

for every two adjacent rows of gate lines in the at least a part of the rows,

outputting a first turn-on signal to a preceding gate line of the two adjacent rows of gate lines in a scanning cycle of the preceding gate line, so that pixel TFTs electrically connected with the preceding gate line can be turned on by the first turn-on signal; and outputting a second turn-on signal to a succeeding gate line of the two adjacent rows of gate lines in a scanning cycle of the succeeding gate line, so that pixel TFTs electrically connected with the succeeding gate line can be turned on by the second turn-on signal, wherein the scanning cycles of these two adjacent rows of gate lines overlap with each other, and the first turn-on signal is opposite in phase to the second turn-on signal.

6. The method according to claim 5 , wherein the scanning cycles of the two rows of adjacent gate lines overlap with each other comprises:

if a first gate line in the array substrate is included in the at least a part of the rows, a scanning cycle of each gate line other than the first gate line in the at least a part of the rows is divided into two periods of time; and signals transmitted on the data lines in the array substrate are data signals displayed by the pixels electrically connected with a previous gate line in a preceding period of the two periods of time; and signals transmitted on the data lines are data signals to be displayed by the pixels electrically connected with the gate line in a succeeding period of the two periods of time.

7. The method according to claim 6 , further comprising:

signals transmitted on the data lines are data signals to be displayed by the pixels electrically connected with the first gate line in a scanning cycle of the first gate line.

8. The method according to claim 6 , further comprising:

a scanning cycle of the first gate line is divided into two periods of time; and signals transmitted on the data lines in the array substrate are preset signals in a preceding period of the two periods of times, and signals transmitted on the data lines in the array substrate are data signals to be displayed by the pixels electrically connected with the first gate line in a succeeding period of the two periods of time.

9. The method according to claim 5 , wherein the scanning cycles of the two adjacent rows of gate lines overlap with each other comprises:

if a first gate line in the array substrate is not included in the at least a part of the rows, a scanning cycle of each gate line in the at least a part of the rows is divided into two periods of time, and signals transmitted on the data lines in the array substrate are data signals displayed by the pixels electrically connected with a previous gate line in a preceding period of the two periods of time; and signals transmitted on the data lines are data signals to be displayed by the pixels electrically connected with the gate line in a succeeding period of the two periods of time.