Resistive memory with small electrode and method for fabricating the same
Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO 2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO 2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO 2 layer over a substrate; fabricating a Al electrode layer over the SiO 2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
1. A resistive memory with a small electrode comprising:
an Al top electrode layer having a reduced effective area forming the small electrode,
a SiO 2 layer,
a Si layer,
a resistive material layer and
a lower electrode layer in sequence,
wherein
the Al top electrode layer and the resistive material layer are electrically connected through one or more conductive channels and
the conductive channels are formed by penetrating of Al material into the Si layer via defects in the SiO 2 layer and dissolving of Si material into the Al material,
wherein the reduced effective area of the Al top electrode layer is formed by the penetrating of the Al material into the Si layer,
wherein the conductive channels are formed as a needle structure that penetrates the SiO 2 layer and the Si layer to the resistive material layer,
wherein the material of the resistive layer is made of hafnium oxide, and
wherein the thickness of the Si layer is larger than 100 nm to prevent the Si material from being totally absorbed by the Al material.
2. The resistive memory according to claim 1 , wherein, the thickness of the Si layer is determined on V/A, wherein, V is a diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.
3. The resistive memory according to claim 2 , wherein, the thickness of the SiO 2 layer is about 100 nm.
4. The resistive memory according to claim 3 , wherein the lower electrode layer is made of Pt.
5. The resistive memory according to claim 2 , wherein the lower electrode layer is made of Pt.
6. The resistive memory according to claim 1 , wherein, the thickness of the SiO 2 layer is about 100 nm.
7. The resistive memory according to claim 6 , wherein the lower electrode layer is made of Pt.
8. The resistive memory according to claim 1 , wherein the lower electrode layer is made of Pt.
9. A method for fabricating a resistive memory with a small electrode, the method comprising:
forming a lower electrode layer and a resistive layer over a substrate;
fabricating a Si layer and a SiO 2 layer over the resistive layer;
fabricating a Al top electrode layer having a reduced effective area forming the small electrode over the SiO 2 layer; and
performing an anneal process to a resultant structure including the Al top electrode layer, the SiO 2 layer, the Si layer, the resistive material layer and the lower electrode layer to form one or more conductive channels between the Al top electrode layer and the resistive layer,
wherein the conductive channels are formed by penetrating of Al material into the Si layer via defects in the SiO 2 layer and dissolving of Si material into the Al material,
wherein the reduced effective area of the Al top electrode layer is formed by the penetrating of the Al material into the Si layer,
wherein the conductive channels are formed as a needle structure that penetrates the SiO 2 layer and the Si layer to the resistive material layer,
wherein the resistive layer is made of hafnium oxide, and
wherein the thickness of the Si layer is larger than 100 nm to prevent Si material from being totally absorbed by the Al material.
10. The method according to claim 9 , wherein, in the step of fabricating the Si layer and the SiO 2 layer, the Si layer is first formed on the resistive layer and then an oxidation process is performed to the Si layer to form the SiO 2 layer.
11. The method according to claim 10 , wherein, the thickness of the Si layer depends on V/A, wherein, V represents the diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.
12. The method according to claim 11 , wherein, the thickness of the SiO 2 layer is about 100 nm.
13. The method according to claim 9 , wherein, the lower electrode layer and the resistive layer are formed by a chemical vapor deposition method; the Si layer is formed by a physical vapor deposition method; the SiO 2 layer is formed by forming a Si layer through a chemical vapor deposition method firstly and then oxidizing the surface of the Si layer through a diffusion process; the Al top electrode layer is formed through an atom layer deposition method.
14. The method according to claim 13 , wherein, the thickness of the Si layer depends on V/A, wherein, V represents the diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.
15. The method according to claim 9 , wherein the lower electrode layer is made of Pt.
16. The method according to claim 15 , wherein, the thickness of the Si layer depends on V/A, wherein, V represents the diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.
17. The method according to claim 9 , wherein, the thickness of the Si layer depends on V/A, wherein, V represents the diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.
18. The method according to claim 17 , wherein, the thickness of the SiO 2 layer is about 100 nm.
19. The method according to claim 9 , wherein the SiO2 layer is formed by forming a Si layer through a chemical vapor deposition method firstly and then oxidizing the surface of the Si layer through a diffusion process.
20. The method according to claim 19 , wherein, the thickness of the Si layer depends on V/A, wherein, V represents the diffusion distance of Si material in Al material and A represents the contact area between Al and Si in the conductive channels.