High-lead count implant device and method of making the same
The invention provides chip packaging and processes for the assembly of retinal prosthesis devices. Advantageously, photo-patternable adhesive or epoxy such as photoresist is used as glue to attach a chip to the targeted thin-film (e.g., parylene) substrate so that the chip is used as an attachment to prevent delamination.
1. A method for fabricating a flexible thin-film substrate for attachment of a device to be implanted, the method comprising:
depositing a first thin-film layer on a silicon-wafer to form a bottom thin-film layer;
depositing a metal to the bottom thin-film layer to form an electrical connection;
depositing a second thin-film layer adjacent to the metal to form a top thin-film layer and to thereby form a thin-film metal thin-film sandwich;
providing a mask adjacent to the second thin-film layer;
directing an etching beam onto the mask to fabricate the flexible thin-film for attachment of the device,
detaching the silicon-wafer from the flexible thin-film substrate and attaching the device, wherein the device is an integrated circuit chip (IC Chip), which electrically connects the flexible thin-film substrate to the IC Chip, and wherein the flexible thin-film substrate and device are encapsulated for biocompatibility.
2. The method of claim 1 , wherein the first thin-film layer and the second thin-film layer are each independently selected from the group consisting of parylene, polyimide, polytetrafluoroethylene (PTFE), poly (4,4′-oxydiphenylene-pyromellitimide) and a printed circuit board (PCB).
3. The method of claim 2 , wherein the first thin-film layer and the second thin-film layer are each parylene.
4. The method of claim 3 , wherein the parylene is a member selected from the group consisting of parylene N, parylene C, parylene D, parylene HT, parylene AM, parylene A and combinations thereof.
5. The method of claim 4 , wherein the parylene is parylene C.
6. The method of claim 1 , wherein the silicon-wafer is treated with 1,1,1,3,3,3-hexamethyldisilazane (HMDS).
7. The method of claim 3 , wherein the first parylene layer is deposited by chemical vapor deposition (CVD).
8. The method of claim 3 , wherein the first parylene layer is between 0.1 μm and 100 μm thick.
9. The method of claim 8 , wherein the first parylene layer is between 1 μm and 10 μm thick.
10. The method of claim 1 , wherein the metal is a conductor selected from the group consisting of Cr/Au, Ni/Au, Ti/Au, Al/Ti, Ag/Ti, Cr/Au/Ti/Ni/Au, Ni/Pd/Au, and Ti/Ni/Au.
11. The method of claim 10 , wherein the metal is Ti/Au.
12. The method of claim 3 , wherein the second parylene layer is deposited by chemical vapor deposition (CVD).
13. The method of claim 12 , wherein the second parylene layer is between 10 μm and 200 μm thick.
14. The method of claim 13 , wherein the second parylene layer is between 20 μm and 60 μm thick.
15. The method of claim 3 , wherein the etching is reactive ion etching (RIE) masked by a metal mask.
16. The method of claim 3 , wherein the etching is deep reactive ion etching (DRIE) masked by a metal mask.
17. The method of claim 15 , wherein the RIE is oxygen plasma etching.
18. The method of claim 3 , wherein the parylene, metal, parylene deposition steps are repeated to generate a plurality of parylene-metal-parylene sandwich layers.
19. The method of claim 1 , wherein the device is integrated with the substrate with an epoxy squeegee connection.
20. The method of claim 1 , wherein the substrate and the device is encapsulated in parylene C.