Interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the dielectric layer; forming a first build-up circuitry and a second build-up circuitry that cover the semiconductor device, the stopper and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.
1. A method of making an interconnect substrate with an embedded device and a built-in stopper, comprising:
forming a stopper on a dielectric layer; which includes: providing a laminate substrate that includes a metal layer and the dielectric layer; and then removing a selected portion of the metal layer to form the stopper;
mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device that includes an active surface with a contact pad thereon and an inactive surface, wherein the active surface faces a first vertical direction, the inactive surface faces a second vertical direction opposite the first vertical direction, and the stopper is located in close proximity to and laterally aligned with and laterally extends beyond peripheral edges of the semiconductor device in lateral directions orthogonal to the vertical directions;
attaching a stiffener to the dielectric layer, including aligning the semiconductor device and the stopper within an aperture of the stiffener;
forming a first build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the first vertical direction and includes a first conductive via that directly contacts the contact pad of the semiconductor device to provide an electrical connection between the semiconductor device and the first build-up circuitry;
forming a second build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the second vertical direction; and
providing a plated through-hole that extends through the stiffener in the vertical directions to provide an electrical connection between the first build-up circuitry and the second build-up circuitry.
2. The method of claim 1 , wherein the electrical connection between the semiconductor device and the first build-up circuitry is devoid of solder.
3. The method of claim 1 , wherein the semiconductor device is mounted on the dielectric layer with the active surface facing the dielectric layer and the stopper extends from the dielectric layer in the second vertical direction.
4. The method of claim 3 , wherein the semiconductor device is attached to the dielectric layer using an adhesive that contacts and is sandwiched between the semiconductor device and the dielectric layer.
5. The method of claim 4 , wherein the adhesive contacts and is coplanar with the stopper in the first vertical direction and is lower than the stopper in the second vertical direction.
6. The method of claim 4 , wherein the forming the first build-up circuitry and the second build-up circuitry includes:
providing a first insulating layer that includes the dielectric layer and covers the stopper, the semiconductor device and the stiffener in the first vertical direction;
providing a second insulating layer that covers the stopper, the semiconductor device and the stiffener in the second vertical direction;
forming a first via opening that extends through the first insulating layer and the adhesive and is aligned with the contact pad of the semiconductor device;
forming a first conductive trace that extends from the first insulating layer in the first vertical direction and extends laterally on the first insulating layer and extends through the first via opening in the second vertical direction to form the first conductive via in direct contact with the contact pad of the semiconductor device; and
forming a second conductive trace that extends from the second insulating layer in the second vertical direction and extends laterally on the second insulating layer.
7. The method of claim 6 , wherein the forming the first build-up circuitry includes:
forming an additional first via opening that extends through the first insulating layer and is aligned with the stiffener; and then
forming the first conductive trace that extends through the additional first via opening in the second vertical direction to form an additional first conductive via in direct contact with the stiffener.
8. The method of claim 6 , wherein the forming the second build-up circuitry includes:
forming second via openings that extend through the second insulating layer and are aligned with the inactive surface of the semiconductor device and the stiffener; and then
forming the second conductive trace that extends through the second via openings in the first vertical direction to form second conductive vias in direct contact with the inactive surface of the semiconductor device and the stiffener.
9. The method of claim 1 , wherein the semiconductor device is mounted on the dielectric layer with the inactive surface facing the dielectric layer and the stopper extends from the dielectric layer in the first vertical direction.
10. The method of claim 9 , the semiconductor device is attached to the dielectric layer using an adhesive that contacts and is sandwiched between the semiconductor device and the dielectric layer.
11. The method of claim 10 , wherein the adhesive contacts and is coplanar with the stopper in the second vertical direction and is lower than the stopper in the first vertical direction.
12. The method of claim 10 , wherein the forming the first build-up circuitry and the second build-up circuitry includes:
providing a first insulating layer that covers the stopper, the semiconductor device and the stiffener in the first vertical direction;
providing a second insulating layer that includes the dielectric layer and covers the stopper, the semiconductor device and the stiffener in the second vertical direction;
forming a first via opening that extends through the first insulating layer and is aligned with the contact pad of the semiconductor device;
forming a first conductive trace that extends from the first insulating layer in the first vertical direction and extends laterally on the first insulating layer and extends through the first via opening in the second vertical direction to form the first conductive via in direct contact with the contact pad of the semiconductor device; and
forming a second conductive trace that extends from the second insulating layer in the second vertical direction and extends laterally on the second insulating layer.
13. The method of claim 12 , wherein the forming the first build-up circuitry includes:
forming an additional first via opening in the first insulating layer that extends through the first insulating layer and is aligned with the stiffener; and then
forming the first conductive trace that extends through the additional first via opening in the second vertical direction to form an additional first conductive via in direct contact with the stiffener.
14. The method of claim 12 , wherein the forming the second build-up circuitry includes:
forming second via openings that extend through the second insulating layer and the adhesive and are aligned with the inactive surface of the semiconductor device and the stiffener; and then
forming the second conductive trace that extends through the second via openings in the first vertical direction to form second conductive vias in direct contact with the inactive surface of the semiconductor device and the stiffener.
15. The method of claim 1 , wherein the providing the plated through-hole includes:
forming a through-hole that extends through the stiffener and the dielectric layer in the vertical directions; and then
depositing a connecting layer on an inner sidewall of the through-hole.
16. The method of claim 1 , wherein the stopper include a continuous or discontinuous strip or an array of posts.
17. The method of claim 1 , wherein a gap in between the semiconductor device and the stopper is in a range of 0.001 to 1 mm.
18. The method of claim 1 , wherein the stopper has a height in a range of 10 to 200 microns.
19. The method of claim 1 , wherein the stiffener is a laminated epoxy or polyimide.
20. The method of claim 1 , wherein the semiconductor device is mounted on the dielectric layer with the inactive surface facing the dielectric layer and the stopper extends from the dielectric layer in the first vertical direction.
21. The method of claim 20 , the semiconductor device is attached to the dielectric layer using an adhesive that contacts and is sandwiched between the semiconductor device and the dielectric layer.
22. The method of claim 21 , wherein the adhesive contacts and is coplanar with the stopper in the second vertical direction and is lower than the stopper in the first vertical direction.
23. The method of claim 20 , wherein the forming the first build-up circuitry and the second build-up circuitry includes:
providing a first insulating layer that covers the stopper, the semiconductor device and the stiffener in the first vertical direction;
providing a second insulating layer that includes the dielectric layer and covers the stopper, the semiconductor device and the stiffener in the second vertical direction;
forming a first via opening that extends through the first insulating layer and is aligned with the contact pad of the semiconductor device;
forming a first conductive trace that extends from the first insulating layer in the first vertical direction and extends laterally on the first insulating layer and extends through the first via opening in the second vertical direction to form the first conductive via in direct contact with the contact pad of the semiconductor device; and
forming a second conductive trace that extends from the second insulating layer in the second vertical direction and extends laterally on the second insulating layer.
24. The method of claim 23 , wherein the forming the first build-up circuitry includes:
forming an additional first via opening in the first insulating layer that extends through the first insulating layer and is aligned with the stiffener; and then
forming the first conductive trace that extends through the additional first via opening in the second vertical direction to form an additional first conductive via in direct contact with the stiffener.
25. The method of claim 23 , wherein the forming the second build-up circuitry includes:
forming second via openings that extend through the second insulating layer and the adhesive and are aligned with the inactive surface of the semiconductor device and the stiffener; and then
forming the second conductive trace that extends through the second via openings in the first vertical direction to form second conductive vias in direct contact with the inactive surface of the semiconductor device and the stiffener.
26. A method of making an interconnect substrate with an embedded device and a built-in stopper, comprising:
forming a stopper on a dielectric layer; which includes: providing a laminate substrate that includes a metal layer and the dielectric layer; then removing a selected portion of the metal layer to form a recessed portion; then depositing a plastic material into the recessed portion; and then removing a remaining portion of the metal layer;
mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device that includes an active surface with a contact pad thereon and an inactive surface, wherein the active surface faces a first vertical direction, the inactive surface faces a second vertical direction opposite the first vertical direction, and the stopper is located in close proximity to and laterally aligned with and laterally extends beyond peripheral edges of the semiconductor device in lateral directions orthogonal to the vertical directions;
attaching a stiffener to the dielectric layer, including aligning the semiconductor device and the stopper within an aperture of the stiffener;
forming a first build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the first vertical direction and includes a first conductive via that directly contacts the contact pad of the semiconductor device to provide an electrical connection between the semiconductor device and the first build-up circuitry;
forming a second build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the second vertical direction; and
providing a plated through-hole that extends through the stiffener in the vertical directions to provide an electrical connection between the first build-up circuitry and the second build-up circuitry.
27. The method of claim 26 , wherein the electrical connection between the semiconductor device and the first build-up circuitry is devoid of solder.
28. The method of claim 26 , wherein the semiconductor device is mounted on the dielectric layer with the active surface facing the dielectric layer and the stopper extends from the dielectric layer in the second vertical direction.
29. The method of claim 28 , wherein the semiconductor device is attached to the dielectric layer using an adhesive that contacts and is sandwiched between the semiconductor device and the dielectric layer.
30. The method of claim 29 , wherein the adhesive contacts and is coplanar with the stopper in the first vertical direction and is lower than the stopper in the second vertical direction.
31. The method of claim 29 , wherein the forming the first build-up circuitry and the second build-up circuitry includes:
providing a first insulating layer that includes the dielectric layer and covers the stopper, the semiconductor device and the stiffener in the first vertical direction;
providing a second insulating layer that covers the stopper, the semiconductor device and the stiffener in the second vertical direction;
forming a first via opening that extends through the first insulating layer and the adhesive and is aligned with the contact pad of the semiconductor device;
forming a first conductive trace that extends from the first insulating layer in the first vertical direction and extends laterally on the first insulating layer and extends through the first via opening in the second vertical direction to form the first conductive via in direct contact with the contact pad of the semiconductor device; and
forming a second conductive trace that extends from the second insulating layer in the second vertical direction and extends laterally on the second insulating layer.
32. The method of claim 31 , wherein the forming the first build-up circuitry includes:
forming an additional first via opening that extends through the first insulating layer and is aligned with the stiffener; and then
forming the first conductive trace that extends through the additional first via opening in the second vertical direction to form an additional first conductive via in direct contact with the stiffener.
33. The method of claim 31 , wherein the forming the second build-up circuitry includes:
forming second via openings that extend through the second insulating layer and are aligned with the inactive surface of the semiconductor device and the stiffener; and then
forming the second conductive trace that extends through the second via openings in the first vertical direction to form second conductive vias in direct contact with the inactive surface of the semiconductor device and the stiffener.
34. The method of claim 26 , wherein the providing the plated through-hole includes:
forming a through-hole that extends through the stiffener and the dielectric layer in the vertical directions; and then
depositing a connecting layer on an inner sidewall of the through-hole.
35. The method of claim 26 , wherein the stopper include a continuous or discontinuous strip or an array of posts.
36. The method of claim 26 , wherein a gap in between the semiconductor device and the stopper is in a range of 0.001 to 1 mm.
37. The method of claim 26 , wherein the stopper has a height in a range of 10 to 200 microns.
38. The method of claim 26 , wherein the stiffener is a laminated epoxy or polyimide.