IP Library Granted Patent US 9,147,638
Granted Patent B2
US 9,147,638 · App. 13/951,122 · Granted Sep 29, 2015

Interconnect structures for embedded bridge

Inventors: Yueli Liu (Chandler, AZ); Chong Zhang (Chandler, AZ); Qinglei Zhang (Chandler, AZ)
Assignee: Intel Corporation
H01L23/48H01L21/50H01L24/13H01L24/16H01L2224/13101H01L2224/16225H01L2924/15192
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Quick Facts
Patent No.
US 9,147,638
App. No.
13/951,122
Granted
Sep 29, 2015
Kind
B2
Abstract

Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed.

Claims (26)

1. A package assembly comprising:

a bridge interconnect structure including a die contact and electrical routing features to route electrical signals between a first die and a second die;

an electrically insulative layer disposed on the bridge interconnect structure; and

a die interconnect of the first die or the second die disposed on and electrically coupled with the die contact, the die interconnect including a pillar structure that extends through the electrically insulative layer and protrudes beyond a surface of the electrically insulative layer.

2. The package assembly of claim 1 , wherein the pillar structure has a tapered profile.

3. The package assembly of claim 1 , wherein the die interconnect further includes a solderable material disposed on the pillar structure.

4. The package assembly of claim 3 , wherein no pad structure intervenes between the pillar structure and the solderable material.

5. The package assembly of claim 1 , wherein the bridge interconnect structure comprises a semiconductor material.

6. The package assembly of claim 1 , wherein the electrically insulative layer comprises a build-up layer of a package substrate.

7. The package assembly of claim 1 , the package assembly further comprising:

electrical routing features disposed in the electrically insulative layer and configured to route electrical signals between the first die or the second die and a circuit board.

8. The package assembly of claim 1 , wherein the die interconnect is a first die interconnect of the first die, the package assembly further comprising:

a second die interconnect of the first die, wherein a pitch between the first die interconnect and the second die interconnect is 55 microns or less.

9. A computing device comprising:

a package assembly including

a bridge interconnect structure including a first die contact and a second die contact that are configured to route electrical signals between a first die and a second die,

an electrically insulative layer disposed on the bridge interconnect structure,

a first die interconnect disposed on and electrically coupled with the first die contact,

a second die interconnect disposed on and electrically coupled with the second die contact,

the first die coupled with the first die interconnect, and

the second die coupled with the second die interconnect, wherein the first die interconnect and the second die interconnect each include a pillar structure that extends through the electrically insulative layer and protrudes beyond a surface of the electrically insulative layer; and

a circuit board coupled with at least one of the first die or the second die, using package interconnects.

10. The computing device of claim 9 , further comprising:

electrical routing features disposed in the electrically insulative layer and configured to route electrical signals between each of the first die and the second die and the circuit board.

11. The computing device of claim 9 , wherein:

the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2013
From: LIU, YUELI; ZHANG, QINGLEI; ZHANG, CHONG
To: INTEL CORPORATION
Reel/Frame 030879/0851 →
Continuity (1)
Related Publication 20150028486A1 · Jan 29, 2015