Granted Patent B2

US 9,148,270 · App. 14/196,804 · Granted Sep 29, 2015

Inventor: Yan Wang (Los Gatos, CA)

Assignee: Broadcom Corporation

H04L5/0058G06F3/00G06F9/46G06F13/3625G06F13/4031

Abstract

Claims (76)

1. A method performed by a processing system that comprises at least one interchip interface module, the method comprising:

assigning a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of multiple time slices comprising the first time slice and a second time slice;

identifying a contiguous memory area in a memory element in the interchip interface module;

storing a first data item from the first-type communication channel into the contiguous memory area in response to the first priority being assigned to the first-type communication channel;

identifying communication channels of one or more types other than the first-type comprising one or more data items that fit a remaining portion of the memory element;

arbitrating among the communication channels of one or more types other than the first-type in the second time slice; and

in response to the arbitrating, storing a second data item from one of the communication channels of one or more types other than the first-type in the memory element in the interchip interface module.

2. The method of claim 1 , further comprising:

determining whether or not two or more first-type communication channels are eligible for arbitration during the first time slice of the set of multiple time slices; and

performing scheduling discipline among the two or more first-type communication channels, where the two or more first-type communication channels are determined to be eligible for arbitration.

3. The method of claim 1 , wherein:

the criterion comprises a result of determining whether the first-type communication channel is eligible for arbitration.

4. The method of claim 3 , wherein, when the first-type communication channel is eligible for arbitration, assigning the first priority to the first-type communication channel in the first time slice comprises:

assigning a first weight to the first-type communication channel; and

updating a first register for the first-type communication channel based at least in part upon the first weight.

5. The method of claim 3 , wherein, when the first-type communication channel is ineligible for arbitration in the first time slice, assigning the first priority to the first-type communication channel in the first time slice comprises:

determining whether one or more second-type communication channels are eligible for arbitration during the first time slice;

arbitrating among the one or more second-type communication channels;

storing a second data item from a second-type communication channel of the one or more second-type communication channels in the memory element in the first time slice;

and assigning first priority to the first-type communication channel in the second time slice.

6. The method of claim 3 , wherein, when the first-type communication channel and a second-type communication channel are ineligible for arbitration in the first time slice, assigning the first priority to the first-type communication channel in the first time slice comprises:

determining whether one or more third-type communication channels are eligible for arbitration;

arbitrating among the one or more third-type communication channels;

storing a third data item from a third-type communication channel of the one or more third-type communication channels in the memory element in the first time slice;

and assigning the first priority to the first-type communication channel in the second time slice.

7. The method of claim 1 , wherein

the first data item is stored into the contiguous memory area starting at a lowest memory address of the contiguous memory area.

8. The method of claim 1 , wherein arbitrating among the communication channels other than the first-type communication channel in the second time slice comprises:

determining whether one or more second-type communication channels are eligible for arbitration in the second time slice;

determining whether one or more third-type communication channels are eligible for arbitration in the second time slice; and

determining whether one or more first-type communication channels are eligible for arbitration when the one or more second-type communication channels and the one or more third-type communication channels are ineligible for arbitration.

9. The method of claim 8 , wherein determining whether the one or more second-type communication channels is eligible for arbitration in the second time slice comprises:

determining whether the one or more second-type communication channels comprise more than one second-type communication channel;

assigning a second priority to a second-type communication channel of the one or more second-type communication channels based on scheduling discipline; and

storing a second data item in the memory element when at least one of: the one or more third-type communication channels is determined to be eligible for arbitration, and the second-type communication channel is determined to be eligible for arbitration.

10. The method of claim 9 , wherein determining whether the one or more second-type communication channels is eligible for arbitration in the second time slice further comprises:

incrementing one or more counters for the one or more third-type communication channels.

11. The method of claim 9 , wherein storing the second data item in the memory element comprises:

writing the second data item in the memory element starting at a lowest memory address of the memory element.

12. The method of claim 8 , wherein determining whether the one or more second-type communication channels are eligible for arbitration in the second time slice comprises:

determining whether the one or more third-type communication channels comprise more than one third-type communication channel;

assigning a third priority to a third-type communication channel of the one or more third-type communication channels based on scheduling discipline; and

storing a third data item from the third-type communication channel in the memory element.

13. The method of claim 1 , further comprising at least one of:

transmitting, by the at least one interchip interface module, one or more data items from the processing system to another processing system; and

receiving, by the at least one interchip interface module, one or more other data items at the processing system from the another processing system.

14. A processing system, comprising:

an interchip interface module comprising:

an arbitration module configured to assign a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of multiple time slices comprising the first time slice and a second time slice, and to arbitrate among communication channels other than the first-type communication channel in the second time slice;

a memory element for storing a first data item from the first-type communication channel in response to the first priority assigned to the first-type communication channel; and

logic configured to identify a contiguous memory area in a memory element in the interchip interface module, store the first data item into the contiguous memory area in response to the first priority being assigned, and identify one or more communication channels of one or more types other than the first-type comprising one or more data items that fit a remaining portion of the memory element.

15. The processing system of claim 14 , wherein:

the arbitration module is further configured to determine whether the first-type communication channel is eligible for arbitration to assign the first priority.

16. The processing system of claim 15 , wherein, when the first-type communication channel is eligible for arbitration, the arbitration module is further configured to:

assign a first weight to the first-type communication channel, and

update a first register for the first-type communication channel based at least in part upon the first weight.

17. The processing system of claim 15 , wherein, when the first-type communication channel is ineligible for arbitration in the first time slice, the arbitration module is further configured to:

determine whether one or more second-type communication channels are eligible for arbitration;

arbitrate among the one or more second-type communication channels;

store a second data item from a second-type communication channel of the one or more second-type communication channels in the memory element in the first time slice;

and assign the first priority to the first-type communication channel in the second time slice.

18. The processing system of claim 15 , wherein, when the first-type communication channel and a second-type communication channel are ineligible for arbitration in the first time slice, the arbitration module is further configured to:

determine whether one or more third-type communication channels are eligible for arbitration;

arbitrate among the one or more third-type communication channels;

store a third data item from a third-type communication channel of the one or more third-type communication channels in the memory element in the first time slice;

and assign the first priority to the first-type communication channel in the second time slice.

19. The processing system of claim 14 , wherein the arbitration module is further configured to:

determine whether one or more second-type communication channels are eligible for arbitration in the second time slice;

determine whether one or more third type communication channels are eligible for arbitration in the second time slice; and

determine whether one or more first-type communication channels are eligible for arbitration when the one or more second-type communication channels and the one or more third-type communication channels are ineligible for arbitration.

20. The processing system of claim 19 ,

wherein:

the first-type communication channel comprises a 144-bit datapath width;

the second-type communication channel comprises a 64-bit datapath width;

the third-type communication channel comprises a 32-bit datapath width; and

the memory element includes at least five memory banks, each of which comprise a 32-bit datapath width.

Assignments (9)

Continuity (2)