Method of silicon etch for trench sidewall smoothing
Methods of silicon etch for trench sidewall smoothing are described. In one embodiment, a method involves smoothing a sidewall of a trench formed in a semiconductor wafer via plasma etching. The method includes directionally etching the semiconductor wafer with plasma generated from a fluorine gas to smooth the sidewall of the trench, the trench having a protective layer formed by plasma generated by a second process gas such as oxygen or a polymerization gas. In another embodiment, a method involves etching a semiconductor wafer to generate a trench having a smooth sidewall. The method includes plasma etching the semiconductor wafer with one or more first process gases including a fluorine gas, simultaneously performing deposition and plasma etching the semiconductor wafer with one or more second process gases including a fluorine gas and a polymerization gas mix, and performing deposition with one or more third process gases including a polymerization gas.
1. A method of smoothing a sidewall of a trench formed in a semiconductor wafer, the method comprising:
supporting the semiconductor wafer with a pedestal in a processing chamber, the semiconductor wafer comprising the trench;
introducing a fluorine containing gas into the processing chamber;
introducing a polymerization gas into the processing chamber concurrently with the fluorine containing gas;
delivering power to the processing chamber to generate plasma from the fluorine containing gas and the polymerization gas, the plasma generated from the polymerization gas to form a polymer layer on the sidewall of the trench; and
directionally etching the semiconductor wafer with the plasma generated from the fluorine containing gas to smooth the sidewall of the trench with the polymer layer.
2. The method of claim 1 , wherein introducing the polymerization gas into the processing chamber comprises introducing a carbon fluoride gas.
3. The method of claim 2 , wherein
the carbon fluoride gas to form the protective layer on the sidewall of the trench comprises CHF 3 , C 2 F 6 , C 3 F 8 , or C 4 F 8 .
4. The method of claim 1 , wherein delivering the power to the processing chamber comprises applying an RF power source to a plasma source and biasing the semiconductor wafer with a plurality of RF power pulses.
5. The method of claim 4 , wherein applying the RF power source comprises applying power in a range of 500-3000 Watts to the plasma source, and wherein biasing the semiconductor wafer comprises biasing the semiconductor wafer with a plurality of power pulses in a second range of 50-1000 Watts each.
6. The method of claim 1 , wherein the sidewall of the trench comprises scallops, and wherein directionally etching the semiconductor wafer with the plasma generated from the fluorine containing gas comprises removing the scallops from the sidewall of the trench with the polymer layer.
7. The method of claim 6 , wherein the trench formed in the semiconductor wafer comprises a through silicon via (TSV) trench.
8. A method of smoothing a sidewall of a trench formed in a semiconductor wafer, the method comprising:
introducing a fluorine containing gas into a processing chamber in which the semiconductor wafer is supported, the semiconductor wafer comprising the trench;
introducing a polymerization gas into the processing chamber concurrently with the fluorine containing gas;
delivering power to the processing chamber to generate plasma from fluorine containing gas and the polymerization gas, the plasma generated from the polymerization gas to form a polymer layer on the sidewall of the trench; and
directionally etching, simultaneously with the formation of the polymer layer, the semiconductor wafer with the plasma generated from the fluorine containing gas to smooth the sidewall of the trench.
9. The method of claim 8 , wherein introducing the polymerization gas into the processing chamber comprises introducing a carbon fluoride gas.
10. The method of claim 9 , wherein
the carbon fluoride gas to form the polymer layer on the sidewall of the trench comprises CHF 3 , C 2 F 6 , C 3 F 8 , or C 4 F 8 .
11. The method of claim 8 , wherein delivering the power to the processing chamber comprises applying an RF power source to a plasma source and biasing the semiconductor wafer with a plurality of RF power pulses.
12. The method of claim 11 , wherein applying the RF power source comprises applying power in a range of 500-3000 Watts to the plasma source, and wherein biasing the semiconductor wafer comprises biasing the semiconductor wafer with a plurality of power pulses in a second range of 50-1000 Watts each.
13. The method of claim 8 , wherein the sidewall of the trench comprises scallops, and wherein directionally etching the semiconductor wafer with the plasma generated from the fluorine containing gas comprises removing the scallops from the sidewall of the trench with the polymer layer.
14. The method of claim 13 , wherein the trench formed in the semiconductor wafer comprises a through silicon via (TSV) trench.