IP Library Granted Patent US 9,159,656
Granted Patent B2
US 9,159,656 · App. 14/019,351 · Granted Oct 13, 2015

Semiconductor die package and method for making the same

Inventors: Oseob Jeon (Seoul, KR); Yoonhwa Choi (Inchun, KR); Boon Huan Gooi (Penang, MY); Maria Cristina B. Estacio (Cebu, PH); David Chong (Penang, MY); Tan Teik Keng (Penang, MY); Shibaek Nam (Puchon, KR); Rajeev Joshi (Cupertino, CA); Chung-Lin Wu (San Jose, CA); Venkat Iyer (Redmond, WA); Lay Yeap Lim (Penang, MY); Byoung-Ok Lee (Puchon, KR)
Assignee: Fairchild Semiconductor Corporation
H01L23/49575H01L21/561H01L23/3121H01L23/4951H01L23/49558H01L23/49562H01L23/49861H01L24/29H01L24/32H01L24/39H01L24/49H01L24/83H01L24/97H01L25/0655H01L24/45H01L24/48H01L2223/54406H01L2223/54486H01L2224/16H01L2224/291H01L2224/293H01L2224/2919H01L2224/2929H01L2224/29111H01L2224/29299H01L2224/32057H01L2224/32225H01L2224/456H01L2224/45015H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/45565H01L2224/45644H01L2224/45669H01L2224/48091H01L2224/48137H01L2224/48227H01L2224/48237H01L2224/48247H01L2224/48257H01L2224/48465H01L2224/4943H01L2224/49113H01L2224/73204H01L2224/73265H01L2224/83192H01L2224/83385H01L2224/85013H01L2224/97H01L2924/00013H01L2924/01004H01L2924/014H01L2924/01005H01L2924/0105H01L2924/01006H01L2924/01013H01L2924/01015H01L2924/01019H01L2924/01023H01L2924/01024H01L2924/01027H01L2924/01028H01L2924/01029H01L2924/0132H01L2924/01033H01L2924/01046H01L2924/01047H01L2924/01067H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/07802H01L2924/1305H01L2924/1306H01L2924/13091H01L2924/14H01L2924/15747H01L2924/1815H01L2924/19043H01L2924/30107Y10T29/49121
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Quick Facts
Patent No.
US 9,159,656
App. No.
14/019,351
Granted
Oct 13, 2015
Kind
B2
Abstract

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Claims (14)

1. A semiconductor device package comprising:

a substrate comprising a conductive die attach surface;

a high side transistor including a high side transistor input, wherein the high side transistor input is coupled to the conductive die attach surface;

a low side transistor including a low side transistor output, wherein the low side transistor input is coupled to the conductive die attach surface; and

a controller chip mounted on the substrate and connected to the high side and low side transistors to control their operation.

2. The semiconductor die package of claim 1 further comprising:

an encapsulating material formed around the high side transistor and the low side transistor.

3. The semiconductor die package of claim 1 wherein the high side transistor is a high side MOSFET and the high side transistor input is a high side transistor source connection.

4. The semiconductor die package of claim 1 wherein the low side transistor is a low side MOSFET and the low side transistor output is a low side transistor drain connection.

5. The semiconductor die package of claim 1 wherein the high side transistor is a high side MOSFET and the low side transistor is a low side MOSFET and the low side transistor output is a low side transistor drain connection.

6. The semiconductor die package of claim 1 wherein the conductive die attach surface is part of a leadframe.

7. The semiconductor die package of claim 1 wherein the substrate comprises a molding material that has an exterior surface that is substantially coplanar with the conductive die attach surface.

8. The semiconductor die package of claim 1 wherein the high side transistor has a high side transistor output, wherein the high side transistor output is distal to the conductive die attach surface and the high side transistor input is proximate the conductive die attach surface and wherein the package further comprises a clip or wirebond coupling the high side transistor output to external leads.

9. The semiconductor die package of claim 1 wherein the high side transistor has a high side transistor output, wherein the high side transistor output is distal to the conductive die attach surface and the high side transistor input is proximate the conductive die attach surface and wherein the package further comprises a clip or wirebond coupling the high side transistor output to external leads, and wherein the high and low side transistors are both power MOSFETs.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
Continuity (10)
Division 13430347 · Mar 26, 2012
Division 12823411 · Jun 25, 2010
Division 11471291 · Jun 19, 2006
Provisional Application 60696027 · Jun 30, 2005
Provisional Application 60696305 · Jun 30, 2005
Provisional Application 60696350 · Jun 30, 2005
Provisional Application 60701781 · Jul 22, 2005
Provisional Application 60702076 · Jul 22, 2005
Provisional Application 60753040 · Dec 21, 2005
Related Publication 20140167238A1 · Jun 19, 2014