IP Library › Granted Patent US 9,159,851
Granted Patent B2
US 9,159,851 · App. 13/699,231 · Granted Oct 13, 2015

Photovoltaic structures having a light scattering interface layer and methods of making the same

Inventors: Xiangxin Liu (Beijing, CN); Alvin D. Compaan (Holland, OH); Naba Raj Paudel (Toledo, OH)
Assignee: The University of Toledo
H01L31/02363H01L31/0296H01L31/073H01L31/0749H01L31/1828H01L31/1864Y02E10/52Y02E10/541Y02E10/543
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Quick Facts
Patent No.
US 9,159,851
App. No.
13/699,231
Granted
Oct 13, 2015
Kind
B2
Abstract

Photovoltaic (PV) cell structures having an integral light scattering interface layer configured to diffuse or scatter light prior to entering a semiconductor material and methods of making the same are described.

Claims (18)

1. A photovoltaic cell comprising:

a first semiconductor layer configured to absorb a first portion of incident light rays and permit a second portion of incident light rays to pass therethrough;

a second semiconductor layer configured to absorb a wavelength range of the second portion of incident light rays, at least one of the first and second semiconductor layers being annealed; and

a light scattering interface region formed within one or more of the first and second semiconductor layers at an interface, the light scattering interface region including inclusions configured as one of particulates and voids, the inclusions configured to scatter a wavelength of one of the first and second portions of incident light rays, the inclusions being formed in the one or more of the first and second semiconductor layers during annealing such that the inclusion size is generally equal to the wavelength range of one of the first and second portions of incident light rays;

wherein the first semiconductor layer is a CdS layer and the second semiconductor layer is a CdTe layer, the CdTe being annealed such that the light scattering interface region is formed in the CdTe layer adjacent to the CdS layer, the light scattering interface region having voids extends from about 20% to about 50% of the CdTe layer thickness,

the first and second semiconductor material layers exhibiting a compressive stress in a plane defined by the first and second semiconductor material layers, and

the light scattering interface region forming a lattice that is elongated in a direction perpendicular to the plane of the first and second semiconductor material layers.

2. The photovoltaic cell of claim 1 , wherein the voids are in a size range of about 0.1 microns to about 1 micron.

3. The photovoltaic cell of claim 1 , wherein the first semiconductor layer is a CdS layer, and the second semiconductor layer is a CdTe layer deposited such that the CdTe layer has a compressive stress.

4. The photovoltaic cell of claim 3 , wherein the CdTe layer has a thickness in the range of 0.2 microns to 2.4 microns.

5. The photovoltaic cell of claim 1 , wherein the CdTe layer is annealed in the presence of CdCl 2 .

6. The photovoltaic cell of claim 1 , wherein the first and second semiconductor layers have a lattice mismatch of about 10%, and the inclusions are voids formed in conjunction with a CdCl 2 annealing process.

7. A photovoltaic cell comprising:

a first semiconductor layer configured to absorb a first portion of incident light rays and permit a second portion of incident light rays to pass therethrough;

a second semiconductor layer configured to absorb a wavelength range of the second portion of incident light rays, at least one of the first and second semiconductor layers being annealed; and

a light scattering interface region formed within one or more of the first and second semiconductor layers at an interface, the light scattering interface region including inclusions configured as one of particulates and voids, the inclusions configured to scatter a wavelength of one of the first and second portions of incident light rays, the inclusions being formed in the one or more of the first and second semiconductor layers during annealing such that the inclusion size is generally equal to the wavelength range of one of the first and second portions of incident light rays;

wherein the first semiconductor layer is a CdS layer, and the second semiconductor layer is a CdTe layer deposited such that the CdTe layer has a compressive stress wherein the CdTe layer has a thickness in the range of 0.2 microns to 2.4 microns; and,

wherein the light scattering interface region is formed within the CdTe layer, the light scattering interface region having a void fraction of about 8%.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2012
From: LIU, XIANGXIN; COMPAAN, ALVIN D.; PAUDEL, NABA RAJ
To: THE UNIVERSITY OF TOLEDO
Reel/Frame 029429/0081 →
Continuity (2)
Provisional Application 61348709 · May 26, 2010
Related Publication 20130206217A1 · Aug 15, 2013