Ring oscillator and semiconductor device
There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.
1. A ring oscillator comprising a plurality of delay circuits to be ring-connected, wherein
at least one of the plurality of delay circuits includes a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element,
the delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to an input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits, and
the path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition, wherein
a signal delayed by one of the delay element or the path circuit of the delay circuit in the previous stage is delayed by the other of the delay element or the path circuit of the delay circuit in the next stage.
2. The ring oscillator according to claim 1 , wherein
the delay element and the path circuit are connected in series across the plurality of stages, respectively, and the delay element and the path circuit output an inverted signal of an input signal as an output signal.
3. The ring oscillator according to claim 1 , wherein
the delay element includes one of an nMOS transistor to the gate of which an input signal is input and the source of which is grounded, and a pMOS transistor to the gate of which an input signal is input and the source of which is connected to a power source.
4. The ring oscillator according to claim 1 , wherein
in a layout region of the SRAM cell, a first transmission transistor, a second transmission transistor, a first pull-up transistor the gate of which is connected to the source of the second transmission transistor and the source of which is connected to a power source, a first pull-down transistor the gate of which is connected to the source of the second transmission transistor, the source of which is grounded, and the drain of which is connected to the source of the first transmission transistor, a second pull-up transistor the gate of which is connected to the drain of the first pull-up transistor, the source of which is connected to a power source, and the drain of which is connected to the source of the second transmission transistor, and a second pull-down transistor the gate of which is connected to the drain of the first pull-up transistor, the source of which is grounded, and the drain of which is connected to the source of the second transmission transistor are laid out, and
the delay element includes the second pull-down transistor.
5. The ring oscillator according to claim 4 , wherein
the connections between the drain of the first pull-down transistor and the respective drains of the first pull-up transistor, the second pull-up transistor, and the second pull-down transistor are opened, and
the opening is implemented by not possessing a via connecting wire layers formed in a layout region having the same layout shape as the layout shape of the SRAM cell.
6. The ring oscillator according to claim 1 , wherein
in a layout region of the SRAM cell, a first transmission transistor, a second transmission transistor, a first pull-up transistor the gate of which is connected to the source of the second transmission transistor, the source of which is opened, and the drain of which is connected to the source of the first transmission transistor, a first pull-down transistor the gate of which is connected to the source of the second transmission transistor, the source of which is grounded, and the drain of which is connected to the source of the first transmission transistor, a second pull-up transistor the gate of which is connected to the source of the first transmission transistor, the source of which is connected to a power source, and the drain of which is connected to the source of the second transmission transistor, and a second pull-down transistor the gate of which is connected to the source of the first transmission transistor, the source of which is grounded, and the drain of which is connected to the source of the second transmission transistor are laid out, and
the delay element includes the second pull-up transistor.
7. The ring oscillator according to claim 6 , wherein
the connection between the source of the first pull-up transistor and the power source is opened, and
the opening is implemented by not possessing a via connecting wire layers formed in a layout region having the same layout shape as the layout shape of the SRAM cell.
8. The ring oscillator according to claim 1 , wherein
the delay element and the path circuit are connected in series to the delay element and the path circuit in the previous stage and to the delay element and the path circuit in the subsequent stage, respectively.
9. The ring oscillator according to claim 1 , wherein
the delay elements are connected in parallel in plurality.
10. A semiconductor device comprising:
an SRAM cell array including a plurality of SRAM cells; and
a ring oscillator comprising a plurality of delay circuits to be ring-connected, wherein:
at least one of the plurality of delay circuits includes a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element,
the delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to an input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits, and
the path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition, wherein
a signal delayed by one of the delay element or the path circuit of the delay circuit in the previous stage is delayed by the other of the delay element or the path circuit of the delay circuit in the next stage.