Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches
Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.
1. A radio-frequency (RF) switch comprising:
first and second field-effect transistors (FETs) connected in series, each of the first and second FETs having a gate node and a body node;
a gate-coupling path that couples the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;
a body-coupling path that couples the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET; and
an adjustable-resistance circuit connected to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a first resistor and a bypass switch.
2. The switch of claim 1 wherein at least one of the first and second FETs is a silicon-on-insulator (SOI) FET.
3. The switch of claim 1 wherein the gate-coupling path further includes a second resistor in series with the first capacitor.
4. The switch of claim 1 wherein the gate-coupling path further includes a second resistor.
5. The switch of claim 3 wherein the body-coupling path further includes a third resistor in series with the second capacitor.
6. The switch of claim 1 wherein the body-coupling path further includes a second resistor.
7. The switch of claim 1 further comprising a switchable resistive coupling circuit connected to the gate nodes of the first and second FETs.
8. The switch of claim 1 further comprising a coupling circuit that couples the respective body and gate of each of the first and second FETs, the coupling circuit including a capacitor electrically parallel with a diode.
9. A semiconductor die comprising:
a semiconductor substrate;
first and second field-effect transistors (FETs) formed on the semiconductor substrate and connected in series, each of the first and second FETs including a gate node and a body node;
a gate-coupling path formed on the semiconductor substrate that couples the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;
a body-coupling path formed on the semiconductor substrate that couples the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET; and
an adjustable resistance circuit connected to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a resistor and a bypass switch.
10. The die of claim 9 further comprising an insulator layer disposed between the first and second FETs and the semiconductor substrate.
11. The die of claim 10 wherein the die is a silicon-on-insulator (SOI) die.
12. A method for fabricating a semiconductor die, the method comprising:
providing a semiconductor substrate;
forming first and second field-effect transistors (FETs) on the semiconductor substrate so as to be connected in series, each of the first and second FETs having a gate node and a body node;
forming a gate-coupling path on the semiconductor substrate to couple the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;
forming a body-coupling path on the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET;
connecting an adjustable-resistance circuit to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a resistor and a bypass switch.
13. The method of claim 12 further comprising forming an insulator layer between the first and second FETs and the semiconductor substrate.