Memory having internal processors and methods of controlling memory access
Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
1. A memory comprising:
a memory array comprising one or more memory banks, wherein the memory array is configured to store data in the one or more memory banks;
an internal processor configured to receive the data stored in the memory array and to perform a first operation on the data; and
a fetch unit configured to receive an instruction comprising an address in the memory array and a command to perform a second operation at the address to facilitate the internal processor perform the first operation, and to substantially control access to the memory array by ensuring only one operation at a time is performed on a specific memory bank comprising the address, wherein the fetch unit is external to the internal processor.
2. The memory of claim 1 , comprising a memory control device communicatively coupled to the fetch unit, wherein the memory control device is configured to receive the command and the address in the memory array from the fetch unit and to decode the command and the address, wherein the memory control is separate from the fetch unit.
3. The memory of claim 1 , wherein the fetch unit is configured to perform the second operation by reading data from the address or writing data to the address.
4. The memory of claim 1 , wherein the fetch unit is configured to perform the second operation by activating and precharging the specific memory bank.
5. The memory of claim 1 , comprising control logic communicatively coupled to the fetch unit, wherein the fetch unit is configured to ensure only one command is performed at a time on the specific memory bank based at least in part on a control signal transmitted to the fetch unit from the control logic indicating that performance of the operation is complete.
6. The memory of claim 1 , comprising a timer communicatively coupled to the fetch unit, wherein the timer is configured to indicate when the specific memory bank is available.
7. The memory of claim 1 , comprising a timer communicatively coupled to the fetch unit, wherein the timer is configured to indicate when the operation has been performed.
8. A memory comprising:
a memory array comprising one or more memory banks, wherein the memory array is configured to store data in the one or more memory banks;
an internal processor configured to receive the data stored in the memory array and to perform a first operation on the data; and
a sequencer configured to retrieve an instruction from an instruction buffer and to transfer the instruction to a fetch unit, wherein the instruction comprises an address in the memory array and a first command to perform a second operation at the address to facilitate the internal processor perform the first operation, the fetch unit is configured to substantially control access to the memory array, and the sequencer is external to the internal processor.
9. The memory of claim 8 , comprising a memory control device communicatively coupled to the fetch unit, wherein the memory control device is configured to receive the first command and the address in the memory array from the fetch unit and to decode the command and the address, wherein the memory control device is separate from the fetch unit.
10. The memory of claim 8 , wherein the instruction comprises a second command to perform a third operation on the memory array, wherein the sequencer is configured to organize performance of the second operation and the third operation.
11. The memory of claim 10 , wherein the instruction comprises a third command describing organization of performance of the second operation and the third operation.
12. A method comprising:
receiving an instruction by a fetch unit of memory, wherein the memory comprises an internal processor configured to receive data stored in the memory and to perform a first operation on the data, the instruction comprises an address in the memory array and a command to perform a second operation at the address, wherein the fetch unit is configured to substantially control access to the memory array;
transferring the instruction from the fetch unit to a memory control device of the memory, wherein the fetch unit is separate from the memory control device;
decoding the instruction into a decoded address and a control signal using the memory control device; and
performing the second operation using the fetch unit based at least in part on the decoded address and the control signal to facilitate the internal processor perform the first operation.
13. The method of claim 12 , wherein the fetch unit and the memory control device are external to the internal processor.
14. The method of claim 12 , comprising receiving a first control signal from control logic indicating that performance of the second operation is complete.
15. The method of claim 14 , comprising receiving a second control signal from the control logic indicating that a memory bank associated with the address has been closed.
16. The method of claim 12 , comprising activating a first timer of the memory, wherein the first timer sets a time when the fetch unit may begin performing the second operation.
17. The method of claim 16 , comprising activating a second timer of the memory, wherein the second timer sets a time when performance of the first second operation is complete.
18. The method of claim 12 , comprising:
sequencing performance of the second operation and a third operation using a sequencer, wherein the sequencer is external to the internal processor; and
performing the third operation using the fetch unit.
19. The method of claim 12 , wherein performing the second operation comprises reading data from the address or writing data to the address using the fetch unit.
20. The method of claim 12 , wherein performing the second operation comprises activating a memory bank corresponding with the address and precharging the memory bank using the fetch unit.