ECC management for variable resistance memory cells
A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.
1. An apparatus comprising first and second variable resistance memory cells physically adjacent on a data storage medium and each having a first error correction code (ECC), a controller configured to upgrade the first ECC of the second variable resistance memory cell to a second ECC level in response to a resistance shift in the first variable resistance memory cell predicted by a model based on a weighted factoring provided by a bloom filter.
2. The apparatus of claim 1 , wherein the at least one variable resistance memory cell is part of a solid-state memory array.
3. The apparatus of claim 2 , wherein the solid-state memory array has a plurality of different types of variable resistance memory cells.
4. The apparatus of claim 3 , wherein a first type of variable resistance memory cell comprises a programmable metallization cell.
5. The apparatus of claim 4 , wherein a second type of variable resistance memory cell comprises a phase change random access memory cell.
6. The apparatus of claim 5 , wherein a third type of variable resistance memory cell comprises a resistive random access memory cell.
7. The apparatus of claim 1 , wherein the controller comprises an evaluation engine configured to concurrently analyze a plurality of different memory cell operational conditions to predict the resistance shift in the first variable resistance memory cell.
8. The apparatus of claim 7 , wherein the evaluation engine provides a model generator with data to predict the resistance shift in the first variable resistance memory cell.
9. The apparatus of claim 1 , wherein the predicted resistance shift in the first variable resistance memory cell corresponds with no predicted resistance shift the second variable resistance memory cell.
10. A method comprising predicting a resistance shift in a first variable resistance memory cell with a model based on a weighted factoring provided by a bloom filter and upgrading a first error correction code (ECC) level of a second variable resistance memory cell to a second ECC level, the first and second variable resistance memory cells being physically adjacent on a data storage medium and each having a first ECC prior to the upgrading step.
11. The method of claim 10 , wherein the first ECC level comprises a checksum.
12. The method of claim 11 , wherein the second ECC level comprises a parity check.
13. The method of claim 10 , wherein the second ECC level comprises a different ECC scheme than the first ECC level.
14. The method of claim 10 , wherein the controller uses a plurality of different operational parameters to generate a predicted model of variations in memory cell resistances.
15. The method of claim 14 , wherein the predicted model is used by an ECC engine to predict ECC for predetermined memory cells.
16. The method of claim 10 , wherein the first ECC level corresponds to a page of variable resistance memory cells and the second ECC level corresponds to an individual variable resistance memory cell.
17. A method comprising predicting a resistance shift in a first variable resistance memory cell with a model based on a weighted factoring provided by a bloom filter and proactively upgrading a first error correction code (ECC) level of the first variable resistance memory cell to a second ECC level and the first ECC level of a second variable resistance memory cell to a third ECC level, the first and second variable resistance memory cells being physically adjacent on a data storage medium, the first, second, and third ECC levels being different.
18. The method of claim 17 , wherein a non-identified variable resistance memory cell logically proximal the first variable resistance memory cell is upgraded to from the first ECC level to the second ECC level.
19. The method of claim 17 , wherein a non-identified variable resistance memory cell physically proximal the first variable resistance memory cell is upgraded to from the first ECC level to the second ECC level.
20. The method of claim 17 , wherein the first ECC level is predicted in response to observed operational data from an evaluation engine portion of the controller.