Nonvolatile memory device comprising page buffer and operation method thereof

1. A nonvolatile memory device, comprising:

a cell array including a plurality of memory cells;

a page buffer unit including a plurality of page buffers and configured to perform a program verification operation in order to sense whether programming of selected memory cells is completed, and each of the plurality of page buffers includes a first data latch and a second data latch; and

a control logic configured to provide a set pulse for setting the first data latch and the second data latch of each of the plurality of page buffers to a program inhibit state according to a result of the program verification operation, the control logic providing the set pulse to at least two of the plurality of page buffers simultaneously such that the first data latch of a first one of the at least two of the plurality of page buffers and the second data latch of a second one of the at least two of the plurality of page buffers are set at the same time.

2. The nonvolatile memory device of claim 1 , wherein each of the plurality of page buffers further comprises a sensing latch for latching data corresponding to the result of the program verification operation.

3. The nonvolatile memory device of claim 2 , wherein the control logic further provides a plurality of set pulses for setting the first data latch and the second data latch of the page buffers during a clock cycle.

4. The nonvolatile memory device of claim 1 , wherein for each of the plurality of page buffers,

the first data latch is configured to store a first bit to be programmed at a corresponding memory cell; and

the second data latch is configured to store a second bit to be programmed at the corresponding memory cell.

5. The nonvolatile memory device of claim 4 , wherein the set pulse is simultaneously provided as a first latch set signal for setting the first data latch of the first one of the at least two of the plurality of page buffers and as a second latch set signal for setting the second data latch of the second one of the at least two of the plurality of page buffers.

6. The nonvolatile memory device of claim 4 , wherein the first bit corresponds to a most significant bit (MSB) of multiple bits to be programmed at the corresponding memory cell and the second bit is another one of the multiple bits.

7. The nonvolatile memory device of claim 4 , wherein the control logic is configured to provide a first pulse stream for setting the first data latches of the page buffers and a second pulse stream for setting the second data latches of the page buffers.

8. The nonvolatile memory device of claim 7 , wherein the first pulse stream is provided during a first clock cycle period and the second pulse stream is provided during a second clock cycle period, the second clock cycle period following the first clock cycle period.

9. A nonvolatile memory device, comprising:

a first page buffer including a first most significant bit (MSB) data latch and a first least significant bit (LSB) data latch;

a second page buffer including a second most significant bit (MSB) data latch and a second least significant bit (LSB) data latch; and

a control logic configured to control the first page buffer and the second page buffer by applying a set pulse simultaneously to both the first most significant bit (MSB) page buffer and the second least significant bit (LSB) page buffer, and

the first page buffer is configured to store first most significant bit (MSB) data in the first most significant bit (MSB) data latch in response to the set pulse, and

the second page buffer is configured to store second least significant bit (LSB) data in the second least significant bit (LSB) data latch in response to the set pulse.

10. The nonvolatile memory device of claim 9 , wherein

the first page buffer includes a first sensing latch, and the first page buffer is configured to store the first most significant bit (MSB) data in the first most significant bit (MSB) data latch according to the first most significant bit (MSB) data stored in the first sensing latch; and

the second page buffer includes a second sensing latch, and the second page buffer is configured to store the second least significant bit (LSB) data in the second least significant bit (LSB) data latch according to the second least significant bit (LSB) data stored in the second sensing latch.

11. The nonvolatile memory device of claim 10 , wherein the first page buffer and the second page buffer are each configured to maintain a target state in response to the set pulse.

12. The nonvolatile memory device of claim 10 , wherein the control logic is further configured to set the first page buffer and the second page buffer to a program inhibit state if a result of a program verification operation indicates that a programming operation has been completed.

13. The nonvolatile memory device of claim 12 , wherein

the first sensing latch is configured to store the first most significant bit (MSB) data corresponding to the result of the program verification operation, and

the second sensing latch is configured to store the second least significant bit (LSB) data corresponding to the result of the program verification operation.

14. The nonvolatile memory device of claim 12 , wherein the first most significant bit (MSB) data latch is configured to store most significant bit (MSB) data of the first page buffer and the second data latch is configured to store least significant bit (LSB) data of the second page buffer.