IP Library Granted Patent US 9,165,922
Granted Patent B2
US 9,165,922 · App. 14/015,986 · Granted Oct 20, 2015

Semiconductor device

Inventors: Akira Yoshioka (Kanagawa, JP); Yasunobu Saito (Tokyo, JP); Hidetoshi Fujimoto (Kanagawa, JP); Takeshi Uchihara (Saitama, JP); Naoko Yanase (Tokyo, JP); Toshiyuki Naka (Kanagawa, JP); Tetsuya Ohno (Kanagawa, JP); Tasuku Ono (Kanagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/0629H01L27/095H01L2224/48091H01L2224/48137H01L2224/73265H01L2924/12032
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Quick Facts
Patent No.
US 9,165,922
App. No.
14/015,986
Granted
Oct 20, 2015
Kind
B2
Abstract

According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

Claims (46)

1. A semiconductor device, comprising:

a conductive substrate;

a field-effect transistor mounted on the conductive substrate, the field-effect transistor including:

a transistor substrate;

a buffer layer disposed on the substrate;

a first semiconductor layer disposed on the buffer layer;

a second semiconductor layer disposed on the first semiconductor layer;

a source electrode disposed on the second semiconductor layer;

a drain electrode disposed on the second semiconductor layer, spaced apart from the source electrode; and

a gate electrode disposed between the source electrode and the drain electrode, and spaced apart from the source electrode and the drain electrode; and

a Schottky barrier diode mounted on the conductive substrate, the Schottky barrier diode including:

an anode electrode electrically connected to the conductive substrate;

a n-type semiconductor substrate disposed on the anode electrode;

a third semiconductor layer disposed on the n-type semiconductor substrate and having a resistance that is higher than a resistance of the n-type semiconductor substrate; and

a cathode electrode disposed on the third semiconductor layer;

wherein the source electrode is electrically connected to the cathode electrode and the gate electrode is electrically connected to the anode electrode.

2. The semiconductor device of claim 1 , wherein the transistor substrate has a resistivity greater than or equal to 100 Ωcm.

3. The semiconductor device of claim 1 , further comprising a heatsink connected to the conductive substrate.

4. The semiconductor device of claim 1 , wherein the conductive substrate comprises a conductive foil on an insulating material.

5. The semiconductor device of claim 1 , wherein the source electrode is electrically connected to the cathode with a first bonding wire, and the gate electrode is electrically connected to the anode electrode with a second bonding wire.

6. The semiconductor device of claim 1 , wherein the Schottky barrier diode is mounted on the conductive substrate using a conductive resin paste, and the field effect transistor is mounted on the conductive substrate using an insulating resin paste.

7. The semiconductor device of claim 1 , wherein the n-type semiconductor substrate and the third semiconductor layer comprise silicon.

8. The semiconductor device of claim 1 , further comprising:

a first external terminal electrically connected to the conductive substrate; and

a second external terminal electrically connected to the drain electrode.

9. The semiconductor device of claim 1 , wherein the field-effect transistor is a high-electron mobility transistor.

10. The semiconductor device of claim 1 , further comprising a gate insulating layer between the gate electrode and the second semiconductor layer.

11. A power semiconductor device, comprising:

a conductive substrate;

a field-effect transistor mounted on the conductive substrate, the field-effect transistor including:

a transistor substrate;

a buffer layer disposed on the substrate;

a first semiconductor layer disposed on the buffer layer, the first semiconductor layer comprising a first nitride semiconductor material;

a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising a second nitride semiconductor material;

a source electrode disposed on the second semiconductor layer;

a drain electrode disposed on the second semiconductor layer, spaced apart from the source electrode; and

a gate electrode disposed between the source electrode and the drain electrode, and spaced apart from the source electrode and the drain electrode; and

a Schottky barrier diode mounted on the conductive substrate, the Schottky barrier diode including:

an anode electrode electrically connected to the conductive substrate;

a n-type semiconductor substrate disposed on the anode electrode;

a third semiconductor layer disposed on the n-type semiconductor substrate and having a resistance that is higher than a resistance of the n-type semiconductor substrate; and

a cathode electrode disposed on the third semiconductor layer;

wherein the source electrode is electrically connected to the cathode electrode, the gate electrode is electrically connected to the anode electrode, the conductive substrate is electrically connected to a first external terminal, and the drain electrode is electrically connected to a second external terminal.

12. The power semiconductor device of claim 11 , wherein the first nitride semiconductor material is gallium nitride and the second nitride semiconductor material is aluminum gallium nitride.

13. The power semiconductor device of claim 11 , wherein the transistor substrate is conductive.

14. The power semiconductor device of claim 11 , further comprising a gate insulating layer between the gate electrode and the second semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2014
From: YOSHIOKA, AKIRA; SAITO, YASUNOBU; FUJIMOTO, HIDETOSHI; UCHIHARA, TAKESHI; YANASE, NAOKO; NAKA, TOSHIYUKI; OHNO, TETSUYA; ONO, TASUKU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 032032/0511 →
Priority Claims (1)
JP 2013-059343 · Mar 22, 2013 · national
Continuity (1)
Related Publication 20140284610A1 · Sep 25, 2014