Image sensor with pixel units having mirrored transistor layout
An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region. A first pixel transistor region of the first pixel unit has a plurality of pixel transistors. A second pixel transistor region of the second pixel unit is horizontally adjacent to the first pixel transistor region and also has a plurality of pixel transistors. A transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region.
1. An image sensor comprising:
a first pixel unit having a first plurality of photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second plurality of photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and
a second pixel transistor region of the second pixel unit, horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;
wherein:
a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region,
the pixel transistor regions each include a reset transistor, a row select transistor, and a source-follower transistor, and
the reset transistor of the first pixel transistor region is disposed adjacent to the reset transistor of the second pixel transistor region and the reset transistors are both coupled to the same shared reset voltage supply connection.
2. The image sensor of claim 1 , wherein the minor image is taken about a vertical line separating the first pixel unit from the second pixel unit.
3. The image sensor of claim 1 , wherein each pixel unit has no more than one shared floating diffusion region.
4. The image sensor of claim 1 , wherein each of the plurality of photodiodes includes no more and no less than four photodiodes.
5. The image sensor of claim 1 , further comprising:
a third pixel unit, horizontally adjacent to the second pixel unit, having a third plurality of photodiodes and a third shared floating diffusion region; and
a third pixel transistor region of the third pixel unit, horizontally adjacent to the second pixel transistor region, having a plurality of pixel transistors for reading out image data from the third shared floating diffusion region,
wherein a transistor layout of the third pixel transistor region is a minor image of the transistor layout of the second pixel transistor region.
6. The image sensor of claim 1 , further comprising:
a third pixel unit, horizontally adjacent to the second pixel unit, having third photodiode region of no more and no less than four photodiodes and a third shared floating diffusion region; and
a third pixel transistor region of the third pixel unit, vertically displaced outside of the third photodiode region and horizontally adjacent to the second pixel transistor region, the third pixel transistor region having a reset transistor, a row select transistor, and a source-follower transistor,
wherein a transistor layout of the third pixel transistor region is a minor image of the transistor layout of the second pixel transistor region, taken about a vertical line separating the second pixel unit from the third pixel unit.
7. A complementary metal oxide semiconductor (CMOS) image sensor comprising:
a first pixel unit having a first photodiode region of no more and no less than four photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second photodiode region of no more and no less than four photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit, vertically displaced outside of the first photodiode region and having a reset transistor, a row select transistor, and a source-follower transistor; and
a second pixel transistor region of the second pixel unit, vertically displaced outside of the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a reset transistor, a row select transistor, and a source-follower transistor,
wherein:
a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, taken about a vertical line separating the first pixel unit from the second pixel unit, and
the source-follower transistor of the first pixel transistor region is disposed adjacent to the source follower transistor of the second pixel transistor region and the source follower transistors are both coupled to the same shared source follower voltage supply connection.
8. The image sensor of claim 7 , wherein the reset transistor of the first pixel transistor region is disposed adjacent to the reset transistor of the second pixel transistor region and wherein the reset transistors are both coupled to the same shared reset voltage supply connection.
9. The image sensor of claim 7 , wherein each pixel unit has no more than one shared floating diffusion region.
10. A complementary metal oxide semiconductor (CMOS) image sensor comprising:
a first pixel unit having a first photodiode region of no more and no less than four photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second photodiode region of no more and no less than four photodiodes and a second shared floating diffusion region;
a third pixel unit, horizontally adjacent to the second pixel unit, having third photodiode region of no more and no less than four photodiodes and a third shared floating diffusion region;
a first pixel transistor region of the first pixel unit, vertically displaced outside of the first photodiode region and having a row select transistor and a source-follower transistor;
a second pixel transistor region of the second pixel unit, vertically displaced outside of the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a row select transistor and a source-follower transistor;
a third pixel transistor region of the third pixel unit, vertically displaced outside of the third photodiode region and horizontally adjacent to the second pixel transistor region, the third pixel transistor region having a row select transistor and a source-follower transistor; and
a shared reset transistor that is shared between the first and second pixel transistor regions;
wherein:
a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, taken about a vertical line bisecting the shared reset transistor,
a transistor layout of the third pixel transistor region is a minor image of the transistor layout of the second pixel transistor region, taken about a vertical line separating the second pixel unit from the third pixel unit, and
the source-follower transistor of the second pixel transistor region is disposed adjacent to the source follower transistor of the third pixel transistor region.
11. An image sensor comprising:
a first pixel unit having a first plurality of photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second plurality of photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and
a second pixel transistor region of the second pixel unit, horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;
wherein:
a transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region,
the pixel transistor regions each include a reset transistor, a row select transistor, and a source-follower transistor, and
the source-follower transistor of the first pixel transistor region is disposed adjacent to the source follower transistor of the second pixel transistor region and the source follower transistors are both coupled to the same shared source follower voltage supply connection.
12. The image sensor of claim 11 wherein the mirror image is taken about a vertical line separating the first pixel unit from the second pixel unit.
13. The image sensor of claim 11 wherein each pixel unit has no more than one shared floating diffusion region.
14. The image sensor of claim 11 wherein each of the plurality of photodiodes includes no more and no less than four photodiodes.
15. The image sensor of claim 11 , further comprising:
a third pixel unit, horizontally adjacent to the second pixel unit, having third photodiode region of no more and no less than four photodiodes and a third shared floating diffusion region; and
a third pixel transistor region of the third pixel unit, vertically displaced outside of the third photodiode region and horizontally adjacent to the second pixel transistor region, the third pixel transistor region having a reset transistor, a row select transistor, and a source-follower transistor;
wherein a transistor layout of the third pixel transistor region is a minor image of the transistor layout of the second pixel transistor region, taken about a vertical line separating the second pixel unit from the third pixel unit.
16. An image sensor comprising:
a first pixel unit having a first plurality of photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second plurality of photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and
a second pixel transistor region of the second pixel unit, horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;
wherein:
a transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region, and
the pixel transistor regions each include a row select transistor and a source-follower transistor, and
the image sensor further comprises a shared reset transistor that is shared between the first and second pixel transistor regions and wherein the mirror image is taken about a vertical line bisecting the shared reset transistor.
17. An image sensor comprising:
a first pixel unit having a first plurality of photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second plurality of photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and
a second pixel transistor region of the second pixel unit, horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;
wherein:
a transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region,
the first pixel transistor region is vertically displaced outside of a first photodiode region including the first plurality of photodiodes, and
the second pixel transistor region is vertically displaced outside of a second photodiode region including the second plurality of photodiodes.
18. An image sensor comprising:
a first pixel unit having a first plurality of photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second plurality of photodiodes and a second shared floating diffusion region;
a third pixel unit, horizontally adjacent to the second pixel unit, having a third plurality of photodiodes and a third shared floating diffusion region;
a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region;
a second pixel transistor region of the second pixel unit, horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;
a third pixel transistor region of the third pixel unit, horizontally adjacent to the second pixel transistor region, having a plurality of pixel transistors for reading out image data from the third shared floating diffusion region;
wherein:
a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region,
a transistor layout of the third pixel transistor region is a mirror image of the transistor layout of the second pixel transistor region, and
a reset transistor of the first pixel transistor region is disposed adjacent to a reset transistor of the second pixel transistor region and a source-follower transistor of the second pixel transistor region is disposed adjacent to a source follower transistor of the third pixel transistor region.
19. A complementary metal oxide semiconductor (CMOS) image sensor comprising:
a first pixel unit having a first photodiode region of no more and no less than four photodiodes and a first shared floating diffusion region;
a second pixel unit, horizontally adjacent to the first pixel unit, having a second photodiode region of no more and no less than four photodiodes and a second shared floating diffusion region;
a first pixel transistor region of the first pixel unit, vertically displaced outside of the first photodiode region and having a reset transistor, a row select transistor, and a source-follower transistor; and
a second pixel transistor region of the second pixel unit, vertically displaced outside of the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a reset transistor, a row select transistor, and a source-follower transistor;
wherein:
a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region taken about a vertical line separating the first pixel unit from the second pixel unit,
the reset transistor of the first pixel transistor region is disposed adjacent to the reset transistor of the second pixel transistor region and the source-follower transistor of the second pixel transistor region is disposed adjacent to the source follower transistor of the third pixel transistor region.