A memory cell ( 32 C), including a first non-insulator ( 34 C) and a second non-insulator ( 40 C), different from the first non-insulator. The second non-insulator forms a junction ( 46 C) with the first non-insulator. The cell further includes a first electrode ( 48 C) which is connected to the first non-insulator and a second electrode ( 50 C) which is connected to the second non-insulator. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.
1. A memory cell, comprising:
a first non-insulator;
a second non-insulator, different from the first non-insulator, forming a rectifying junction with the first non-insulator;
a first electrode connected to the first non-insulator; and
a second electrode connected to the second non-insulator, directly or through one or more additional non-insulators;
wherein at least one of the first and second non-insulators comprises an operational non-insulator having an ionic transference number less than 1 and greater than or equal to 0.5,
wherein the first non-insulator and the second non-insulator are selected so that the junction has electrical rectifying characteristics of a diode junction, and
wherein the diode junction occurs at the interface between the first and second non-insulators.
2. The cell according to claim 1 , wherein the first non-insulator comprises a p-type material having a preponderance of holes, and the second non-insulator comprises an n-type material having a preponderance of electrons, such that the junction between the first and second non-insulators comprises a p-n junction.
3. The cell according to claim 1 , wherein the cell is configurable into one of two different stable electrical states, accessible by an electrical measurement applied to the cell.
4. The cell according to claim 3 , wherein the cell is configured into one of the two different states in response to applying one of a forward and a reverse voltage or current to the cell.
5. The cell according to claim 3 , wherein the cell has a hysteresis in its current-voltage characteristics, so that at a specific voltage the cell has a high-resistance after a first voltage is applied to the cell and a low-resistance after a second voltage is applied to the cell.
6. The cell according to claim 5 , wherein the hysteresis is configured by applying one of a preset voltage and a voltage changing at a preset rate to the cell.
7. The cell according to claim 5 , wherein the one of the two different stable states can be ascertained by measuring a current generated on application of a read voltage between the first and second electrodes.
8. The cell according to claim 3 , wherein the two different stable states have differing open circuit voltages between the first and the second electrodes.
9. The cell according to claim 8 , wherein the one of the two different stable states has a zero open circuit voltage, whereas the other state has a non-zero open circuit voltage.
10. The memory cell according to claim 1 , wherein the one or more additional non-insulators comprise n third non-insulators, where n is an integer greater than or equal to 1, connected sequentially between the second non-insulator and the second electrode to form with the first and second non-insulators (n+1) junctions,
wherein at least one of the first, second and n third non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.
11. The memory cell according to claim 10 , wherein the (n+1) junctions form (n+1) diodes.
12. The memory cell according to claim 10 , wherein the cell has a hysteresis, and wherein the 2 (n+1) stable states are defined by respective hysteresis states of the cell.
13. The memory cell according to claim 10 , wherein the 2 (n+1) stable states have respective 2 (n+1) open circuit voltages.
14. The memory cell according to claim 13 , wherein a first open circuit voltage of the 2 (n+1) open circuit voltages is zero, and wherein a second open circuit voltage is different from zero.
15. A memory array, comprising:
a first non-insulator layer;
a second non-insulator layer, different from the first non-insulator layer, forming a junction layer with the first non-insulator layer;
a first electrode layer connected to the first non-insulator layer;
a second electrode layer connected to the second non-insulator, directly or through one or more additional non-insulators, and configured to define a plurality of memory cells within the array, between respective electrodes in the first and second electrode layers,
wherein at least one of the first and second non-insulator layers is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5,
wherein the first non-insulator and the second non-insulator are selected so that the junction has electrical rectifying characteristics of a diode junction, and
wherein the diode junction occurs at the interface between the first and second non-insulators; and
a processing unit configured to measure an open circuit voltage of at least one of the memory cells and accordingly indicate a value stored by the at least one of the cells.
16. The memory array according to claim 15 , wherein the first non-insulator comprises a mixed ionic electronic conductor and the second non-insulator comprises a non-operational non-insulator.
17. The memory array according to claim 15 , wherein the first and second non-insulator layers comprise epitaxial layers.
18. The memory array according to claim 15 , wherein the first and second non-insulator layers are selected so that the junction layer acts for each cell as a diode, having electrical rectifying characteristics.
19. The memory array according to claim 15 , wherein the first non-insulator comprises a p-type material and the second non-insulator comprises an n-type material.
20. The cell according to claim 1 , wherein the first and second non-insulators comprise non-insulators formed as epitaxial layers.
21. The cell according to claim 1 , wherein the cell is configurable into one of at least three different stable electrical states.
22. The cell according to claim 8 , wherein the two different stable states have different open circuit voltages of different polarities.
23. A method of storing data, comprising:
providing a memory cell including:
a first non-insulator;
a second non-insulator, different from the first non-insulator, forming a junction with the first non-insulator;
a first electrode connected to the first non-insulator;
a second electrode connected to the second non-insulator, directly or through one or more additional non-insulators, wherein the first non-insulator and the second non-insulator are selected so that the junction has electrical rectifying characteristics of a diode junction,
wherein the diode junction occurs at the interface between the first and second non-insulators;
applying to the memory cell a forward or reverse voltage depending on a value to be stored in the cell; and
measuring an open circuit voltage of the cell and accordingly indicating a value stored in the cell.
24. The method of claim 23 , wherein the first and second non-insulators comprise epitaxial non-insulators.
25. The method of claim 23 , wherein the first non-insulator comprises a p-type material and the second non-insulator comprises an n-type material.
26. The cell according to claim 1 , wherein the first non-insulator comprises an operational non-insulator and the second non-insulator comprises a non-operational non-insulator.