IP Library Granted Patent US 9,177,821
Granted Patent B2
US 9,177,821 · App. 14/259,042 · Granted Nov 3, 2015

Method of fabricating electronic circuit

Inventors: Soon-Won Jung (Daejeon, KR); Jae Bon Koo (Daejeon, KR); Chan Woo Park (Daejeon, KR); Bock Soon Na (Daejeon, KR); Sang Chul Lim (Daejeon, KR); Sang Seok Lee (Sejong, KR); Kyoung Ik Cho (Daejeon, KR); Hye Yong Chu (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H01L21/311H01L29/66477
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Quick Facts
Patent No.
US 9,177,821
App. No.
14/259,042
Granted
Nov 3, 2015
Kind
B2
Abstract

Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.

Claims (55)

1. A method of fabricating an electronic circuit, the method comprising:

preparing a substrate including a device region and a wiring region;

forming a polymer film on the substrate;

patterning the polymer film to form a first polymer pattern on the device region of the substrate; and

forming an electronic device on the first polymer pattern;

forming a first metal wiring conformally on the wiring region, the first metal wiring being disposed on an upper surface of the first polymer pattern, between the first polymer pattern and the electronic device.

2. The method of claim 1 , wherein patterning the polymer film comprises:

forming a photoresist pattern on the polymer film;

etching a portion of the polymer film exposed by the photoresist pattern;

selectively removing the photoresist pattern; and

performing a heat treatment process to cure the polymer pattern.

3. The method of claim 1 , wherein the polymer film comprises a polyimide.

4. The method of claim 1 , further comprising forming a second metal wiring disposed on a second surface of the polymer pattern, the second metal wiring being spaced apart from the first metal wiring.

5. The method of claim 4 , wherein the first metal wiring is disposed on a second polymer pattern, electrically connecting the electronic device on the first polymer pattern to an electronic device on the second polymer pattern.

6. The method of claim 1 , wherein forming the electronic device comprises:

forming a source electrode and a drain electrode on the polymer pattern;

forming a semiconductor layer on the source electrode and the drain electrode;

forming a gate insulating layer that covers the source electrode, the drain electrode, and the semiconductor layer; and

forming a gate electrode on the gate insulating layer.

7. The method of claim 1 , wherein the wiring region comprises a repeating array of alternating concave and convex surfaces on a portion of the substrate, the device region being defined by the wiring region,

wherein the repeating array of the alternating concave and convex surfaces of the wiring region is formed after the first polymer pattern is formed.

8. The method of claim 7 , wherein the device region comprises a flat surface.

9. The method of claim 8 , wherein patterning the polymer film comprises forming a photoresist pattern on the device region of the substrate and etching a portion of the polymer film on the wiring region of the substrate by using the photoresist pattern as an etching mask.

10. The method of claim 7 , wherein the device region includes a repeating array of alternating concave and convex surfaces.

11. A method of fabricating an electronic circuit, the method comprising:

preparing a first substrate;

forming a sacrificial film and a polymer film on the substrate;

patterning the polymer film to form a polymer pattern on the sacrificial film;

forming a second substrate covering the polymer pattern on the sacrificial film;

separating the second substrate from the sacrificial film to form the second substrate in which the polymer pattern is embedded; and

forming an electronic device on the polymer pattern.

12. The method of claim 11 , wherein the polymer pattern comprises a cured polyimide.

13. The method of claim 11 , wherein the forming of the second substrate comprises:

applying a stretchable elastomer material on the sacrificial film; and

curing the stretchable elastomer material through a heat treatment process.

14. The method of claim 13 , wherein the stretchable elastomer material comprises a poly-dimethylsiloxane (PDMS).

15. The method of claim 11 , wherein the second substrate comprises a wiring region other than a device region and the device region in which the polymer pattern is formed, and

wherein prior to forming the electronic device, a concave surface and a convex surface are alternately and repeatedly formed on the wiring region of the substrate.

16. The method of claim 15 , further comprising forming a metal wiring on the wiring region of the second substrate,

wherein the metal wiring extends to an upper surface of the polymer to be electrically connected to the electronic device.

17. A method of fabricating an electronic circuit, the method comprising:

preparing a substrate;

forming a polymer film on the substrate;

patterning the polymer film to form a polymer pattern; and

forming an electronic device on the polymer pattern, including:

forming a source electrode and a drain electrode on the polymer pattern;

forming a semiconductor layer on the source electrode and the drain electrode;

forming a gate insulating layer covering the source electrode, the drain electrode, and the semiconductor layer; and

forming a gate electrode on the gate insulating layer.

18. A method of fabricating an electronic circuit, the method comprising:

preparing a substrate including a device region and a wiring region, the device region being defined by the wiring region;

forming a polymer film on the substrate;

patterning the polymer film to form a polymer pattern;

forming a repeating array of alternating concave and convex surfaces on the wiring region after the polymer pattern is formed; and

forming an electronic device on the polymer pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2014
From: JUNG, SOON-WON; KOO, JAE BON; PARK, CHAN WOO; NA, BOCK SOON; LIM, SANG CHUL; LEE, SANG SEOK; CHO, KYOUNG IK; CHU, HYE YONG
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 032749/0787 →
Priority Claims (1)
KR 10-2013-0144635 · Nov 26, 2013 · national
Continuity (1)
Related Publication 20150147854A1 · May 28, 2015