IP Library Granted Patent US 9,177,996
Granted Patent B2
US 9,177,996 · App. 14/072,611 · Granted Nov 3, 2015

Method for forming ReRAM chips operating at low operating temperatures

Inventors: Dipankar Pramanik (Saratoga, CA); Tony P. Chiang (Campbell, CA)
Assignee: Intermolecular, Inc.
H01L27/2418G11C13/0002G11C13/0007G11C13/0069H01L21/0228H01L21/0234H01L21/02183H01L21/02186H01L21/283H01L21/324H01L22/12H01L22/34H01L27/24H01L28/60H01L45/08H01L45/12H01L45/1233H01L45/1253H01L45/1266H01L45/14H01L45/144H01L45/145H01L45/16H01L45/1608H01L45/1616H01L45/1641G11C2013/0083G11C2213/15G11C2213/71G11C2213/77H01L27/2463H01L2924/0002
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Quick Facts
Patent No.
US 9,177,996
App. No.
14/072,611
Granted
Nov 3, 2015
Kind
B2
Abstract

Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Claims (26)

1. A method comprising

forming a memory structure, wherein the memory structure comprises an insulator layer disposed between two electrode layers;

heating the memory structure to a temperature higher than an operating temperature of the memory structure;

applying a first voltage to the two electrode layers to form a switching layer from the insulator layer;

stopping heating the memory structure.

2. A method as in claim 1 wherein the operating temperature is less than 85° C., wherein the forming temperature is between 85° C. and 200° C.

3. A method as in claim 1 wherein heating the memory structure comprises applying a second voltage or current to a heater, wherein the heater is disposed in a vicinity of the memory structure.

4. A method as in claim 1 further comprising

monitoring the temperature of the memory structure after heating.

5. A method as in claim 1 wherein forming a switching layer from the insulator layer comprises forming a filament in the insulator layer.

6. A method comprising

forming a memory chip, wherein the memory chip comprises a memory structure, a heater element and a temperature sensor encapsulated in a chip package, wherein the memory structure comprises an insulator layer disposed between two electrode layers;

applying a first current to the heater element to heat the memory structure to a temperature higher than an operating temperature of the memory structure;

measuring a temperature of the temperature sensor;

applying a second voltage to the two electrode layers to form a switching layer from the insulator layer after the temperature reaches a setpoint temperature;

stopping applying the first current and the second voltage.

7. A method as in claim 6 wherein the memory structure is heated to 100° C. higher than the operating temperature of the memory structure.

8. A method as in claim 6 wherein the operating temperature is less than 85° C., wherein the memory structure is heated to a temperature less than 200° C.

9. A method as in claim 6 wherein heating the memory structure comprises applying a voltage or current to a heater, wherein the heater is disposed in a vicinity of the memory structure.

10. A method as in claim 6 further comprising

monitoring the temperature of the memory structure after heating.

11. A method as in claim 6 wherein forming a switching layer from the insulator layer comprises forming a filament in the insulator layer.

12. A method as in claim 6 wherein the memory structure comprises an array of memory devices, wherein a memory device comprises a switching element disposed between two electrode layers.

13. A method as in claim 12 wherein heating the memory structure comprises heating the array of memory devices.

14. A method as in claim 6 wherein the memory chip is encapsulated with external contact pins.

15. A method as in claim 14 wherein the first current or the second voltage is applied to the memory chip through the external contact pins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2013
From: PRAMANIK, DIPANKAR; CHIANG, TONY P.
To: INTERMOLECULAR, INC.
Reel/Frame 031549/0328 →
Continuity (2)
Provisional Application 61785069 · Mar 14, 2013
Related Publication 20140273300A1 · Sep 18, 2014