IP Library Granted Patent US 9,178,017
Granted Patent B2
US 9,178,017 · App. 14/450,674 · Granted Nov 3, 2015

Semiconductor device and method for manufacturing same

Inventor: Kanta Saino (Tokyo, JP)
Assignee: Micron Technology, Inc.
H01L29/0649H01L27/10814H01L27/10823H01L27/10855H01L27/10876
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Quick Facts
Patent No.
US 9,178,017
App. No.
14/450,674
Granted
Nov 3, 2015
Kind
B2
Abstract

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Claims (32)

1. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate including a first well, a second well, and an isolation region between the first well and the second well with respect to a first direction;

forming a first conductive film which is located on the first well and one end of which in the first direction is positioned on the isolation region, and a second conductive film which is located on the second well and one end of which in the first direction is positioned on the isolation region;

forming a third conductive film, so as to extend from a space on the first conductive film through a space on the isolation region to a space on the second conductive film with respect to the first direction, and have a concave shape on the isolation region;

forming a buried insulating film on the third conductive film, so as to fill a concave portion of the third conductive film on the isolation region;

patterning the first to third conductive films and the buried insulating film to form a first wiring on the first well, a second wiring on the second well, and a concave third wiring and a buried insulating film on the isolation region;

forming an interlayer insulating film on the semiconductor substrate;

removing a portion of the interlayer insulating film until the buried insulating film is exposed;

forming a contact plug, so as to penetrate through the interlayer insulating film, resulting in contacting with at least one of the first and second wells; and

forming a plurality of fourth wirings, so as to contact with the buried insulating film on the third wiring.

2. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the buried insulating film is formed by an ALD method or a low-pressure CVD method in forming the buried insulating film.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a first insulating film by a plasma CVD method between forming the third conductive film and forming the buried insulating film.

4. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a second insulating film on the buried insulating film by a plasma CVD method, following forming the buried insulating film.

5. The method for manufacturing a semiconductor device according to claim 4 ,

wherein the second insulating film is removed in removing the portion of the interlayer insulating film.

6. The method for manufacturing a semiconductor device according to claim 1 , further comprising, between forming the first to third wirings and the buried insulating film and forming the interlayer insulating film:

forming a first source and drain on both sides of the first wiring within the first well; and

forming a second source and drain on both sides of the second wiring within the second well,

wherein a first transistor including the first source and drain and the first wiring as a first gate electrode is formed, and a second transistor including the second source and drain and the second wiring as a second gate electrode is formed.

7. The method for manufacturing a semiconductor device according to claim 6 ,

wherein the first transistor is an N-channel transistor, and the second transistor is a P-channel transistor.

8. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the first well, the second well and the isolation region are located in a peripheral circuit region of the semiconductor substrate,

the method further comprises:

forming a third transistor including a third source and drain in a memory cell region of the semiconductor substrate, between preparing the semiconductor substrate and forming the first to third wirings and the buried insulating film; and

forming a capacitor electrically connected to one of the third source and drain, following forming the fourth wirings.

9. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the first conductive film includes a first metal film and an impurity-containing polysilicon film in order from the side nearest to the semiconductor substrate, and

the second conductive film includes the first metal film and the impurity-containing polysilicon film in order from the side nearest to the semiconductor substrate.

10. The method for manufacturing a semiconductor device according to claim 9 ,

wherein the third conductive film includes the impurity-containing polysilicon film and a second metal film in order from the side nearest to the semiconductor substrate.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2014
From: SAINO, KANTA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033456/0262 →
Priority Claims (1)
JP 2013-171305 · Aug 21, 2013 · national
Continuity (1)
Related Publication 20150054086A1 · Feb 26, 2015