High-efficiency solar-cell arrays with integrated devices and methods for forming them

1. A solar-cell array with integrated bypass diodes, the array comprising:

a substrate;

disposed over the substrate, a plurality of discrete solar cells electrically connected in series to form a series string of discrete solar cells for supplying, under solar illumination, a voltage larger than a voltage produced by any of the discrete solar cells individually, each of the discrete solar cells comprising (i) a first cell comprising a SiGe p-n junction, a SiGe p-i-n junction, a III-V-semiconductor p-n junction, or a III-V-semiconductor p-i-n junction, and (ii) disposed over the first cell, one or more second cells each comprising a III-V-semiconductor p-n junction or a III-V-semiconductor p-i-n junction; and

disposed over the substrate, a plurality of bypass diodes, each bypass diode (i) being associated with a different discrete solar cell, (ii) being discrete and laterally separate from its associated solar cell, and (iii) comprising at least a portion of the first cell without the one or more second cells thereover, a distance between the substrate and the at least a portion of the first cell of the bypass diode being approximately equal to a distance between the substrate and the first cell of the solar cell associated with the bypass diode,

wherein each bypass diode is electrically connected with its associated solar cell such that the bypass diode and the discrete solar cell have opposite polarities.

2. The array of claim 1 , further comprising an isolation diode disposed beneath the first cell, the isolation diode comprising a p-n junction or a p-i-n junction having a polarity opposite a polarity of the first cell.

3. The array of claim 2 , wherein the isolation diode comprises SiGe having a bandgap smaller than a bandgap of the first cell.

4. The array of claim 2 , further comprising a graded-composition layer disposed beneath the first cell, the graded-composition layer relieving at least a portion of a lattice-mismatch strain between the substrate and the first cell.

5. The array of claim 4 , wherein (i) a first portion of the graded-composition layer comprises SiGe and is disposed between the substrate and the isolation diode and (ii) a second portion of the graded-composition layer comprises SiGe and is disposed between the isolation diode and the first cell, the first portion grading from an initial Ge content to an intermediate Ge content larger than the initial Ge content and the second portion grading from approximately the intermediate Ge content to a final Ge content larger than the intermediate Ge content.

6. The array of claim 5 , further comprising a constant-composition SiGe layer disposed between the first and second portions of the graded-composition layer, the constant-composition layer having a Ge content approximately equal to the intermediate Ge content.

7. The array of claim 1 , wherein at least one of the solar cells comprises a silicon cap layer disposed over the one or more second cells.

8. The array of claim 7 , further comprising, for each solar cell, (i) a first contact to the cap layer and (ii) a second contact to a layer disposed beneath the first cell, each of the first and second contacts being disposed over a top surface of the substrate.

9. The array of claim 8 , wherein (i) the first contact comprises a silicide of a metal and (ii) the second contact comprises a germanosilicide of the metal.

10. The array of claim 1 , further comprising, for each bypass diode, (i) a first contact to a top surface of the first cell and (ii) a second contact to a layer disposed beneath the first cell, each of the first and second contacts being disposed over the top surface of the substrate.

11. The array of claim 10 , wherein (i) the first contact comprises a germanosilicide of a metal and (ii) the second contact comprises a germanosilicide of the metal.

12. The array of claim 10 , wherein the first contact covers substantially all of a top surface of the first cell of the bypass diode, thereby substantially preventing solar illumination thereof.

13. The array of claim 1 , further comprising at least one additional series string of discrete solar cells on the substrate, the series string and the at least one additional series string being connected in parallel.

14. The array of claim 1 , further comprising interconnection circuitry on the substrate between each of the plurality of discrete solar cells.

15. The array of claim 14 , wherein the interconnection circuitry between at least two of the discrete solar cells comprises a switching element enabling reconfiguration of the electrical connection between the at least two discrete solar cells.

16. The array of claim 14 , wherein the interconnection circuitry between each of the discrete solar cells comprises a switching element enabling reconfiguration of all of the electrical connections between the discrete solar cells.

17. The array of claim 1 , further comprising, electrically connected to the series string, circuitry for maximum power-point tracking, the circuitry comprising a DC/DC converter.

18. The array of claim 17 , further comprising, electrically connected to the circuitry, a charge-storage element.

19. The array of claim 18 , wherein (i) the circuitry is disposed over a top surface of the substrate and (ii) the charge-storage element is disposed under a bottom surface of the substrate opposite the top surface.

20. The array of claim 1 , further comprising an insulating layer disposed in or above the substrate.

21. The array of claim 1 , wherein the one or more second cells of at least one solar cell are substantially free of Al.

22. The array of claim 1 , wherein, for at least one solar cell, at least one of (i) a boundary between the first cell and the one or more second cells or (ii) a boundary between second cells of the one or more second cells is free of a bonded interface.

23. The array of claim 1 , wherein, for at least one solar cell, the first cell comprises a SiGe p-n junction or a SiGe p-i-n junction.