Circuits and methods for pulse radio receivers

1. A circuit for a pulse radio receiver, comprising:

a radio frequency amplifier that powers off in response to an enable signal;

a demodulator that outputs an RZ signal;

an all-digital clock and data recovery circuit comprising:

a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode,

a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and

a numerical controlled oscillator that receives the loop filter output and produces the enable signal.

2. The circuit of claim 1 , further comprising a low noise amplifier, a second radio frequency amplifier, a mixer, and a programmable gain amplifier, wherein the low noise amplifier generates a first output that is amplified by the radio frequency amplifier to produce a second output, and the second radio frequency amplifier amplifies the second output to produce a third output, the mixer mixes the second output and the third output to produce a fourth output, the programmable gain amplifier amplifies the fourth output to produce a fifth output, and the demodulator receives the fifth output.

3. The circuit of claim 2 , wherein the radio frequency amplifier includes:

a signal transconductor that is coupled to the first output;

a first gyrator transconductor that is coupled to an output of the signal transconductor; and

a second gyrator transconductor that is coupled to an output of the first gyrator transconductor and produces a differential output as the second output.

4. The circuit of claim 3 , wherein the second radio frequency amplifier includes:

a pair of signal transconductors that receive the differential output of the radio frequency amplifier;

a first gyrator transconductor that is coupled to outputs of the pair of signal transconductors;

a second gyrator transconductor that is coupled to outputs from the first gyrator transconductor and that produces the third output.

5. The circuit of claim 2 , wherein the radio frequency amplifier includes:

a signal transconductor with an input that is coupled to the first output and that produces one leg of a differential output that is used as the first output;

an LC bank coupled to an output of the signal transconductor and a second leg out the differential output; and

a negative resistance coupled to the output of the signal transconductor and the second leg of the differential output.

6. The circuit of claim 2 , wherein the second radio frequency amplifier includes:

a pair of signal transconductors coupled to the differential output of the radio frequency amplifier that each has an output that is one leg of a differential output that is the third output;

an LC bank coupled to the outputs of the pair of signal transconductors; and

a negative resistance coupled to the outputs of the pair of signal transconductors.

7. The circuit of claim 2 , wherein the demodulator includes:

a first slicer that compares the fifth output to a coarse threshold to produce a track output;

an integrator coupled to the fifth output that produces an integrator output;

a peak detector that receives the track output and the integrator output and that produces a recovered threshold; and

a second slicer that receives the integrator output and the recovered threshold and that produces the RZ signal.

8. The circuit of claim 7 , wherein the first slicer includes a differential difference comparator.

9. A method of operating a pulse radio receiver, comprising:

powering off a radio frequency amplifier in response to an enable signal;

outputting an RZ signal from a demodulator;

using an all-digital clock and data recovery circuit to:

using a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode to receive the RZ signal and output a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode,

using a loop filter to receive the phase detector output from the phase detector and produce a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and

using a numerical controlled oscillator to receive the loop filter output and produce the enable signal.

10. The method of claim 9 , further comprising:

using a low noise amplifier to generate a first output that is amplified by the radio frequency amplifier to produce a second output;

using a second radio frequency amplifier to amplify the second output to produce a third output;

using a mixer to mix the second output and the third output to produce a fourth output;

using a programmable gain amplifier to amplify the fourth output to produce a fifth output; and

using the demodulator to receive the fifth output.

11. The method of claim 10 , wherein the radio frequency amplifier includes:

a signal transconductor that is coupled to the first output;

a first gyrator transconductor that is coupled to an output of the signal transconductor; and

a second gyrator transconductor that is coupled to an output of the first gyrator transconductor and produces a differential output as the second output.

12. The method of claim 11 , wherein the second radio frequency amplifier includes:

a pair of signal transconductors that receive the differential output of the radio frequency amplifier;

a first gyrator transconductor that is coupled to outputs of the pair of signal transconductors;

a second gyrator transconductor that is coupled to outputs from the first gyrator transconductor and that produces the third output.

13. The method of claim 10 , wherein the radio frequency amplifier includes:

a signal transconductor with an input that is coupled to the first output and that produces one leg of a differential output that is used as the first output;

an LC bank coupled to an output of the signal transconductor and a second leg out the differential output; and

a negative resistance coupled to the output of the signal transconductor and the second leg of the differential output.

14. The method of claim 10 , wherein the second radio frequency amplifier includes:

a pair of signal transconductors coupled to the differential output of the radio frequency amplifier that each has an output that is one leg of a differential output that is the third output;

an LC bank coupled to the outputs of the pair of signal transconductors; and

a negative resistance coupled to the outputs of the pair of signal transconductors.

15. The method of claim 10 , wherein the demodulator includes:

a first slicer that compares the fifth output to a coarse threshold to produce a track output;

an integrator coupled to the fifth output that produces an integrator output;

a peak detector that receives the track output and the integrator output and that produces a recovered threshold; and

a second slicer that receives the integrator output and the recovered threshold and that produces the RZ signal.

16. The method of claim 15 , wherein the first slicer includes a differential difference comparator.