IP Library › Granted Patent US 9,183,977
Granted Patent B2
US 9,183,977 · App. 13/452,669 · Granted Nov 10, 2015

Method for fabricating a coil by way of a rounded trench

Inventors: Markus Menath (Regensburg, DE); Thomas Fischer (Regensburg, DE); Hermann Wendt (Regensburg, DE)
Assignee: Infineon Technologies AG
H01F17/02H01F17/0006H01F41/042H01L21/76816H01L23/5227H01L23/64H01L28/10H01L21/0274H01L21/76804H01L21/76877H01L23/5283H01L27/08H01L2224/48095H01L2224/48137Y10T29/4902
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Quick Facts
Patent No.
US 9,183,977
App. No.
13/452,669
Granted
Nov 10, 2015
Kind
B2
Abstract

A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Claims (31)

1. A method for manufacturing a transformer, the method comprising:

forming a first coil supported by a substrate;

forming a dielectric layer over the substrate and the first coil; and

forming a second coil in the dielectric layer substantially aligned with the first coil, wherein forming the second coil comprises:

forming an opening in the dielectric layer;

forming sidewall spacers along sidewalls of the opening in the dielectric layer, wherein each of the sidewall spacers comprises a first major surface contacting and facing a sidewall of the opening and an opposite, exposed second major surface;

forming an extended opening using an isotropic wet etching so as to expose the first major surfaces of the sidewall spacers and the second major surfaces of the sidewall spacers up to a top surface of the dielectric layer;

removing the sidewall spacers; and

forming a conductive material in the extended opening.

2. The method according to claim 1 , further comprising forming a conductive liner in the extended opening.

3. The method according to claim 1 , wherein the dielectric layer is a single dielectric layer.

4. The method according to claim 1 , wherein forming the extended opening using the isotropic wet etching comprises a substantially homogenous isotropic wet etching of the dielectric layer.

5. A method for manufacturing a device, the method comprising:

forming a dielectric layer over a substrate, the dielectric layer having a top surface facing away from the substrate; and

forming a coil in the dielectric layer, wherein forming the coil comprises:

forming an opening extending into the dielectric layer from the top surface of the dielectric layer;

forming spacers along sidewalls of the opening in the dielectric layer each of the spacers comprising first sidewalls facing the opening and opposite second sidewalls facing the dielectric layer;

forming an extended opening using an isotropic wet etching so as to expose the first sidewalls and the second sidewalls up to the top surface of the dielectric layer;

removing the spacers after forming the extended opening; and

forming a conductive material in the extended opening.

6. The method according to claim 5 , further comprising forming a conductive liner in the extended opening.

7. The method according to claim 5 , wherein the dielectric layer is a single dielectric layer.

8. The method according to claim 5 , wherein forming the extended opening using the isotropic wet etching comprises a substantially homogenous isotropic wet etching of the dielectric layer.

9. The method according to claim 5 , wherein forming spacers along sidewalls of the opening in the dielectric layer comprises depositing polycrystalline silicon and performing an anisotropic etching process to form the spacers comprising the polycrystalline silicon.

10. The method according to claim 5 , wherein forming spacers along sidewalls of the opening in the dielectric layer comprises depositing silicon oxide and performing an anisotropic etching process to form the spacers comprising the silicon oxide.

11. The method according to claim 5 , wherein forming spacers along sidewalls of the opening in the dielectric layer comprises depositing silicon nitride and performing an anisotropic etching process to form the spacers comprising the silicon nitride.

12. The method according to claim 5 , wherein forming spacers along sidewalls of the opening in the dielectric layer comprises depositing photoresist and performing an anisotropic etching process to form the spacers comprising the photoresist.

13. The method according to claim 5 , wherein forming spacers along sidewalls of the opening in the dielectric layer comprises depositing a metal layer and performing an anisotropic etching process to form the spacers comprising the metal layer.

14. The method according to claim 5 , wherein the isotropic wet etching comprises applying a fluorine based etching chemistry.

15. The method according to claim 14 , wherein fluorine based etching chemistry comprises a HF based etching chemistry.

16. The method according to claim 5 , wherein forming the extended opening comprises forming curved sidewalls in a lower region having a first radius of curvature and forming curved sidewalls in an upper region having a second radius of curvature, the first radius of curvature being larger than the second radius of curvature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2012
From: MENATH, MARKUS; FISCHER, THOMAS; WENDT, HERMANN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 028549/0931 →
Continuity (1)
Related Publication 20130277797A1 · Oct 24, 2013