Three-dimensional non-volatile memory device
A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.
1. A semiconductor device, comprising:
at least one first conductive layer stacked in a stacking direction on a substrate where a cell region and a contact region are defined;
at least one first slit passing through the first conductive layer in the stacking direction;
a plurality of second conductive layers stacked in the stacking direction on the first conductive layer;
first and second channel layers each passing through the first and second conductive layers in the stacking direction;
a second slit passing through the first and second conductive layers in the stacking direction, connected with one side of the first slit and located between the first and second channel layers; and
a third slit passing through the first and second conductive layers in the stacking direction and connected with an other side of the first slit,
wherein each of the second conductive layers is connected between the second and third slits and over the first slit.
2. The semiconductor device of claim 1 , wherein the second slit is located in the cell region, and the third slit is located in the contact region.
3. The semiconductor device of claim 1 , wherein the first conductive layer is divided into a plurality of patterns by the first to third slits.
4. The semiconductor device of claim 1 , wherein each of the second conductive layers has a shape of a plate including openings formed by the second and third slits.
5. The semiconductor device of claim 1 , further comprising:
a first source layer formed under the first conductive layer;
a trench formed in the first source layer;
a second source layer formed in the trench and coupled to the channel layers;
a fourth slit located between the channel layers and passing through the trench; and
a third source layer formed in the second source layer and a lower portion of the fourth slit, wherein the third source layer passes through the second source layer and is coupled to the first source layer.
6. The semiconductor device of claim 1 , further comprising:
an insulating layer formed under the first conductive layer;
a trench formed in the insulating layer;
a first source layer formed in the trench and coupled to the channel layers;
a second source layer formed in the first source layer; and
a fourth slit located between the channel layers and coupled to the trench.
7. The semiconductor device of claim 5 , further comprising fifth slits passing through the first conductive layer and coupled to the fourth slit, wherein the fifth slits are located in the contact region.
8. The semiconductor device of claim 7 , wherein the first conductive layer is divided by the first to fifth slits into a plurality of patterns.
9. The semiconductor device of claim 7 , wherein each of the second conductive layers has a shape of a plate including openings formed by the second to fourth slits.
10. The semiconductor device of claim 7 , further comprising sixth slits crossing the fifth slits and passing through the first and second conductive layers.
11. The semiconductor device of claim 10 , wherein the sixth slits have various lengths.
12. The semiconductor device of claim 10 , wherein the sixth slits are located in the contact regions.
13. The semiconductor device of claim 10 , wherein the sixth slits substantially have a linear shape extending in one direction, a linear shape having at least one protruding portion, or a “U” shape.
14. The semiconductor device of claim 6 , wherein the fourth slit is located substantially at the center of the trench.
15. The semiconductor device of claim 6 , wherein ends of the fourth slit are widened substantially forming an I-shape.
16. The semiconductor device of claim 1 , further comprising seventh slits located at a boundary between neighboring memory blocks and passing through the first and second conductive layers.
17. The semiconductor device of claim 16 , wherein each of the seventh slits is formed around each of the memory blocks and connected with the third slit.
18. The semiconductor device of claim 1 , wherein the first conductive layer is a lower selection gate; at least one uppermost second conductive layer, among the second conductive layers, is an upper selection gate; and remaining second conductive layers are control gates.
19. The semiconductor device of claim 1 , wherein the second slit and the third slit are arranged in a line or a staggered configuration.
20. The semiconductor device of claim 1 , wherein the first slit has a bent linear shape.