IP Library Granted Patent US 9,196,604
Granted Patent B2
US 9,196,604 · App. 14/409,301 · Granted Nov 24, 2015

Power semiconductor module having pattern laminated region

Inventors: Yoshiko Tamada (Tokyo, JP); Seiji Oka (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L25/072H01L23/049H01L23/145H01L23/15H01L23/24H01L23/3107H01L23/3675H01L23/3735H01L23/3736H01L23/4334H01L23/49811H01L24/49H01L25/18H05K1/05H01L24/29H01L24/32H01L24/45H01L24/48H01L24/73H01L2224/04042H01L2224/291H01L2224/32225H01L2224/45015H01L2224/45124H01L2224/45147H01L2224/48091H01L2224/48137H01L2224/48139H01L2224/48227H01L2224/4911H01L2224/49175H01L2224/73265H01L2924/1033H01L2924/10253H01L2924/10254H01L2924/10272H01L2924/1203H01L2924/1305H01L2924/13055H01L2924/13091H01L2924/15787H01L2924/1815H01L2924/3011H01L2924/30107H05K1/053H05K3/284H05K2203/1316
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Quick Facts
Patent No.
US 9,196,604
App. No.
14/409,301
Granted
Nov 24, 2015
Kind
B2
Abstract

A power semiconductor module includes a base plate as a metallic heat dissipating body, a first insulating layer on the base plate, and a first wiring pattern on the first insulating layer. On a predetermined region that is a part of the first wiring pattern, a second wiring pattern for a second layer is laminated via only a second insulating layer made of resin, thereby forming a pattern laminated region. A power semiconductor element is mounted in a region other than the pattern laminated region on the first wiring pattern. The base plate, the first insulating layer, the first wiring pattern, the second insulating layer, the second wiring pattern, and the power semiconductor element are integrally sealed with a transfer mold resin, thus obtaining the power semiconductor module.

Claims (19)

1. An insulated power semiconductor module, which contains a plurality of power semiconductor elements therein, the insulated power semiconductor module comprising:

a base plate as a metallic heat dissipating body;

a first insulating layer provided on the base plate; and

a first wiring pattern provided on the first insulating layer, wherein

a predetermined region on the first wiring pattern is a pattern laminated region in which a second wiring pattern for a second layer is laminated via only a second insulating layer made of resin.

2. The insulated power semiconductor module according to claim 1 , wherein the plurality of power semiconductor elements are provided in a region other than the pattern laminated region, on the first wiring pattern.

3. The insulated power semiconductor module according to claim 1 , wherein

the plurality of power semiconductor elements include a self-arc-extinguishing semiconductor element having a gate electrode, an input electrode, and an output electrode, and

one of wiring for the gate electrode and wiring for control of the output electrode of the self-arc-extinguishing semiconductor element is formed in the first wiring pattern, and the other one is formed in the second wiring pattern, so that the wiring for the gate electrode and the wiring for control of the output electrode are laminated in the pattern laminated region.

4. The insulated power semiconductor module according to claim 1 , wherein

the plurality of power semiconductor elements include a self-arc-extinguishing semiconductor element having a gate electrode, an input electrode, and an output electrode, and

a third wiring pattern for a third layer is laminated on the second wiring pattern via only a third insulating layer, and a fourth wiring pattern for a fourth layer is laminated on the third wiring pattern via only a fourth insulating layer, and

one of wiring for the gate electrode and wiring for control of the output electrode of the self-arc-extinguishing semiconductor element is formed in the third wiring pattern, and the other one is formed in the fourth wiring pattern, so that the wiring for the gate electrode and the wiring for control of the output electrode are laminated.

5. The insulated power semiconductor module according to claim 1 , wherein

the first wiring pattern and the second wiring pattern are connected to an input/output electrode and a gate electrode of the power semiconductor element, and the first wiring pattern and the second wiring pattern are insulated.

6. The insulated power semiconductor module according to claim 1 , wherein the first insulating layer is made of resin.

7. The insulated power semiconductor module according to claim 1 , wherein the first insulating layer is made of ceramic.

8. The insulated power semiconductor module according to claim 1 , wherein the plurality of power semiconductor elements include an element formed by a wide bandgap semiconductor.

9. The insulated power semiconductor module according to claim 8 , wherein a material of the wide bandgap semiconductor is silicon carbide, gallium nitride, or diamond.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: TAMADA, YOSHIKO; OKA, SEIJI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 034549/0487 →
Priority Claims (1)
JP 2012-160113 · Jul 19, 2012 · national
Continuity (1)
Related Publication 20150115288A1 · Apr 30, 2015