LDMOS CHC reliability

1. A process of forming an integrated circuit, comprising the steps:

forming an STI trench pattern on a substrate of the integrated circuit;

etching an STI trench into the substrate;

growing a first STI liner oxide on an upper active corner of the STI trench;

stripping a portion of the first STI liner oxide using dilute HF; and

growing a second STI liner oxide on the upper active corner of the STI trench.

2. The process of claim 1 , wherein the substrate is <100> silicon.

3. The process of claim 1 , wherein the substrate is <110> silicon.

4. The process of claim 1 , wherein the first STI liner oxide thickness is in the range of 2 nm and 50 nm, the first STI liner oxide is grown in an ambient of steam or dry O 2 with HCl or chlorine, and the first STI liner oxide is grown at a temperature in the range of 700° C. to 1100° C.

5. The process of claim 1 , wherein the second STI liner oxide thickness is in the range of 5 nm and 50 nm and wherein the second STI liner oxide is grown in an ambient of steam or dry O 2 with HCl or chlorine and is grown at a temperature in the range of 700° C. to 1100° C.

6. A process of forming an integrated circuit, comprising the steps:

forming an STI trench pattern on a substrate of the integrated circuit;

etching an STI trench into the substrate;

growing a first STI liner oxide;

stripping a portion of the first STI liner oxide using dilute HF;

growing a second STI liner oxide;

wherein the first STI liner oxidation grows 11 nm oxide at 800° C. in steam plus HCl, and where 2 nm of the first STI liner oxide is deglazed using 0.5% HF, and where the second STI liner oxidation grows 17.5 nm oxide in dry O 2 plus HCl at 900° C.

7. A process of forming an integrated circuit, comprising the steps:

forming an STI trench pattern on a substrate of the integrated circuit;

etching an STI trench into the substrate;

growing a first STI liner oxide;

stripping a portion of the first STI liner oxide using dilute HF;

growing a second STI liner oxide;

filling the STI trench with STI dielectric;

planarizing the STI dielectric to form a STI geometry;

forming a lightly doped drain photo resist pattern on the integrated circuit with an opening that contains the STI trench;

implanting dopant to form a lightly doped drain where the lightly doped drain contains the STI geometry;

growing a gate oxide on the lightly doped drain and on the substrate; and

forming a gate of a LDMOS transistor wherein the gate overlies the transition region from gate oxide on the lightly doped drain to the STI dielectric.

8. The process of claim 7 , wherein the substrate is p-type, the lightly doped drain is n-type and the LDMOS transistor is an LDNMOS transistor.

9. The process of claim 7 , wherein the substrate is n-type the lightly doped drain is p-type and the LDMOS transistor is a LDPMOS transistor.

10. A process of forming an integrated circuit, comprising the steps:

providing a <110> substrate for the integrated circuit;

forming an STI trench pattern on a substrate of the integrated circuit;

etching an STI trench into the substrate;

growing a first STI liner oxide on an upper active corner of the STI trench;

stripping a portion of the first STI liner oxide using dilute HF;

growing a second STI liner oxide on the upper active corner;

filling the STI trench with STI dielectric;

planarizing the STI dielectric to form an STI geometry;

forming a lightly doped drain photo resist pattern on the substrate with an opening that contains the STI geometry;

implanting dopant to form a lightly doped drain where the lightly dope drain contains the STI geometry;

growing a gate dielectric on the lightly doped drain region adjacent to the STI geometry and on the substrate;

depositing gate material on the gate dielectric and on the STI geometry;

forming a gate photoresist pattern on the gate material where a first portion of the gate pattern overlies gate dielectric on the substrate, where a second portion of the gate pattern overlies gate dielectric on the lightly doped drain, and where a third portion of the gate photoresist pattern overlies a portion of the STI geometry;

etching the gate material to form a gate of an LDMOS transistor; and

removing the gate photoresist pattern.

11. The process of claim 10 , wherein the step of growing the first STI liner oxide grows oxide with a thickness in the range of 2 nm and 50 nm in an ambient of steam or dry O 2 with HCl or chlorine and at a temperature in the range of 700° C. to 1100° C.

12. The process of claim 10 , wherein the step of growing the second STI liner oxide grows oxide with a thickness is in the range of 5 nm and 50 nm in an ambient of steam or dry O 2 with HCl or chlorine and at a temperature in the range of 700° C. to 1100° C.

13. The process of claim 10 , wherein the step of growing the first STI liner oxidation grows 11 nm of oxide at 800° C. in steam plus HCl, and where the step of stripping removes 2 nm of the first STI liner oxide using 0.5% HF, and where the step of growing the second STI liner oxidation grows 17.5 nm oxide in dry O 2 plus HCl at 900° C.

14. The process of claim 10 , wherein the substrate is p-type, the dopant is n-type, the lightly doped drain is n-type, and the LDMOS is an LDNMOS transistor.

15. The process of claim 10 , wherein the substrate is n-type, the dopant is p-type, the lightly doped drain is p-type, and the LDMOS is a LDPMOS transistor.