Trench high electron mobility transistor device

1. A transistor device, comprising:

a crystalline silicon substrate member;

a first substantially flat surface formed on the substrate member;

a second oppositely disposed surface formed on the substrate member and spaced from the first surface;

a third surface formed on the substrate member and extending from the first surface and following a 111 orientation plane;

a source structure formed in the first surface;

a gate structure formed in the first surface and spaced from the source structure;

a drain structure formed on the second surface;

a dielectric layer formed on the first surface;

a p-well formed in the first surface and positioned between the gate structure and the source structure;

wherein the dielectric layer is between about 10 microns thick and about 200 microns thick; and

wherein the third surface hosts a 2-dimensional electron gas.

2. The device of claim 1 wherein the second surface is substantially parallel to the first surface.

3. The device of claim 1 wherein a second dielectric layer is formed over the second surface.

4. The device of claim 1 and further comprising a fourth surface formed on the substrate member and extending from the first surface and following a 111 orientation plane; wherein the fourth surface intersects the third surface; and wherein the intersection of the third and fourth surfaces defines a first volume having a V-shaped cross-sectional shape.

5. The device of claim 4 and further comprising a dielectric wedge filling the first volume.

6. The device of claim 1 and further comprising a metallization layer positioned between the dielectric layer and the first surface.

7. The device of claim 6 and further comprising a first low-temperature oxide layer positioned between the source structure and the metallization layer and a second low-temperature oxide layer positioned between the gate structure and the metallization layer.

8. The device of claim 1 and further comprising a first N-type buffer layer positioned on the first surface between the p-well and the third surface.

9. The device of claim 1 and further comprising a second N-type buffer layer positioned on the second surface.

10. A transistor device, comprising:

a semiconducting substrate having a generally flat top surface and a generally parallel spaced bottom surface, wherein each surface has a [110] or [100] orientation;

a first device surface extending from the top surface towards the bottom surface and having a [111] orientation;

a two-dimensional electron gas formed on the device surface;

a drain contact operationally connected to the two-dimensional electron gas and formed on the bottom surface;

a source contact formed on the top surface and operationally connected to the two-dimensional electron gas;

a gate contact formed on the top surface and operationally connected to the two-dimensional electron gas; and

a gate formed on the first device surface and operationally connected to the two-dimensional electron gas.

11. The transistor device of claim 10 wherein the semiconducting substrate is silicon.

12. The transistor device of claim 11 and further comprising:

a nucleation layer formed on the device surface;

a buffer layer formed on the nucleation layer;

an generally GaN layer formed on the buffer layer and defining a two-dimensional electron gas;

a cap layer formed on the generally GaN layer; and

a metal layer formed over the cap layer.

13. The transistor device of claim 12 wherein the nucleation layer is an AlN/GaM composition; wherein the nucleation layer is between about 1KÅ and about 3KÅ thick; wherein the buffer layer is Al x Ga y N, with 0≦x≦1, 0≦y≦1, and x+y=1; wherein the buffer layer is between about 1 μm and about 5 μm thick; wherein the generally GaN layer is Al 0.25 Ga 0.75 N layer; wherein the generally GaN layer is between about 100 Å and about 500 Å thick; wherein the cap layer is undoped GaN; wherein the cap layer is between about 10 Å and about 20 Å thick; wherein the metal layer is layered Ti/Al/Au; wherein the Ti layer is about 1 KÅ thick; wherein the AL layer is about 2 KÅ thick; and wherein the Au layer is about 1 KÅ thick.

14. The device of claim 10 and further comprising a second device surface spaced from and positioned opposite the first device surface; wherein the second device surface extends from the top surface towards the bottom surface; wherein the second device surface has a [111] orientation; and wherein the first and second device surfaces define a first trough formed in the substrate having a generally V-shaped cross-section.

15. The device of claim 14 and further comprising a plurality of troughs having generally V-shaped cross-sections formed in the substrate.

16. The device of claim 15 wherein the plurality of troughs are oriented generally parallel to one another.

17. A solid state device comprising:

a semiconducting substrate having a generally flat top surface and a generally parallel spaced bottom surface;

a first device surface extending from the top surface towards the bottom surface;

a second device surface spaced from and positioned opposite first device surface and extending from the top surface towards the bottom surface;

a respective two-dimensional electron gas formed on the respective device surfaces;

a drain contact operationally connected to each respective two-dimensional electron gas and positioned on the bottom surface;

a source contact positioned on the top surface and operationally connected to each respective two-dimensional electron gas;

a gate contact positioned on the top surface and operationally connected to each respective two-dimensional electron gas;

a first gate formed on the first device surface and operationally connected to each respective two-dimensional electron gas;

a second gate formed on the second device surface and operationally connected to each respective two-dimensional electron gas;

wherein the first and second device surfaces define a trench having a V-shaped cross-section.

18. The solid state device of claim 17 wherein the substrate is silicon and wherein each respective device surface has a [111] orientation.

19. The solid state device of claim 17 wherein each respective two dimensional electron gas is confined to a respective Al x Ga y N layer formed on each respective device surface; wherein each respective Al x Ga y N layer is between about 100 and about 500 Angstrom units thick.

20. The solid state device of claim 19 wherein x=0.25 and y=0.75.