Reset of processing core in multi-core processing system
This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.
1. A processor comprising:
a plurality of processing cores;
an interconnect coupled to the plurality of processing cores; and
a first logic to detect a non-responding processing core from the plurality of processing cores and to transmit reset information to the non-responding processing core on the interconnect, wherein the reset information is to be formatted into a packet, wherein the reset information includes a reset operation to power-off the non-responsive processing core and unreset information to power-on the non-responsive processing core.
2. The processor as recited in claim 1 , further comprising a second logic to maintain processing of at least one other processing core of the plurality of processing cores while the first logic detects and transmits the reset information to the non-responding processing core to reset the non-responding processing core.
3. The processor as recited in claim 1 , further comprising a second logic to transmit a notification message to at least one other processing core of the plurality of processing cores, the notification message to instruct the at least one other processing core to stop transmitting requests to the non-responding processing core until the non-responding processing core is reset.
4. The processor as recited in claim 3 , wherein the second logic transmits a second notification message to the at least one other processing core to indicate that the at least one other processing core is to resume transmitting the requests.
5. The processor as recited in claim 1 , wherein a first logic detects the non-responding processing core by detecting that the non-responsive processing core has failed to respond to a pending request within a threshold amount of time.
6. The processor as recited in claim 1 , wherein the interconnect is arranged as a ring structure.
7. A method comprising:
formatting a packet to include reset information; and
transmitting the packet over an interconnect to a particular processing core from among a plurality of processing cores, wherein the reset information includes information to at least power-off the particular processing core without powering-off all the plurality of processing cores.
8. The method as recited in claim 7 , further comprising processing instructions by at least one other processing core of the plurality of processing cores while performing the transmitting to reset the particular processing core.
9. The method as recited in claim 7 , further comprising transmitting a notification message to at least one other processing core of the plurality of processing cores, the notification message to instruct the at least one other processing core to drop requests to the particular processing core at least until the particular processing core is reset.
10. The method as recited in claim 9 , further comprising transmitting a second notification message to the at least one other processing core to indicate that the at least one other processing core is to resume transmitting the requests to the particular processing core.
11. The method as recited in claim 7 , wherein the particular processing core is to be reset following an indication that the particular processing core is unresponsive to at least one request for the particular processing core.
12. The method as recited in claim 7 , wherein the interconnect is arranged as a ring structure to facilitate the transmitting of the packet.
13. A method comprising:
detecting a non-responding processing core from a plurality of processing cores by transmitting a test request to the non-responding processing core and detecting the non-responding core is to be reset when the non-responding core does not satisfy conditions of the test;
sending a notice over an interconnect to remaining processing cores in the plurality of processing cores to instruct the remaining processing cores to cease requests of the non-responding processing core; and
transmitting a reset information over the interconnect to the non-responding processing core, wherein the reset information is to be formatted into a packet.
14. The method as recited in claim 13 , further comprising processing instructions by at least some of the remaining processing cores while performing the transmitting the reset information to the non-responding processing core.
15. The method as recited in claim 13 , wherein the notice is formatted into one or more packets for transmission to each of the remaining processing cores.
16. The method as recited in claim 13 , wherein the packet is transmitted from an initialization core to the non-responding core via the interconnect.
17. The method as recited in claim 13 , further comprising monitoring the non-responsive processing core following the transmitting to ensure that the non-responsive core returns to normal operation.