System for execution of security related functions
An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data.
1. An apparatus comprising:
a first memory circuit configured to read or write data to or from a host;
an arithmetic logic circuit communicatively coupled to said first memory circuit, said arithmetic logic circuit comprising a plurality of arithmetic modules each configured to be enabled or disabled in response to control signals received from said first memory circuit and each having a number of multipliers proportional to a size of a public key; and
a plurality of second memory circuits configured to read or write data to or from said first memory circuit through a data exchange layer having a separate read channel and a separate write channel, wherein said arithmetic modules provide cryptographic protection of said data by generating results of two or more arithmetic operations to implement said public key.
2. The apparatus according to claim 1 , wherein said public key includes at least one of a Diffie Hellman Key Exchange function, an RSA function, and an elliptic curve cryptography function.
3. The apparatus according to claim 1 , wherein said apparatus is configured to provide functional and performance debugging during simulation and after hardware is designed.
4. The apparatus according to claim 1 , wherein said apparatus is configured to provide scalability to implement a plurality of key lengths.
5. The apparatus according to claim 4 , wherein said scalability provides a trade-off between performance and gate count.
6. The apparatus according to claim 1 , wherein said cryptographic protection is accelerated by implementing a software architecture.
7. The apparatus according to claim 6 , wherein said software architecture is configured to transparently accelerate targeted cryptographic functions.
8. The apparatus according to claim 1 , wherein said apparatus includes a single code base configured to seamlessly instantiate a high performance and low gate count design.
9. The apparatus according to claim 1 , wherein said apparatus includes a firmware implemented with a high level software programming language to operate said apparatus.
10. The apparatus according to claim 9 , wherein said high level software programming language comprises C.
11. The apparatus according to claim 1 , wherein said apparatus is configured to implement parallelism.
12. The apparatus according to claim 1 , wherein said arithmetic modules operate on 8192 bit numbers.
13. The apparatus according to claim 1 , wherein said apparatus is configured to provide an efficient pipeline architecture.
14. The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
15. The apparatus according to claim 1 , wherein said firmware implements a command FIFO for facilitating communications between the host and the arithmetic logic circuit.
16. The apparatus according to claim 15 , wherein said plurality of second memory circuits includes a plurality of targets, and for each target said data exchange layer implements at least one of a read FIFO control or a write FIFO instruction.
17. The apparatus according to claim 1 , wherein said plurality of second memory circuits comprise connected memory circuits and disconnected memory circuits, and wherein said data exchange layer facilitates communication to both connected and disconnected memory circuits.
18. The apparatus according to claim 1 , wherein said plurality of arithmetic modules include one or more carry and save adders and more than four multipliers.
19. A computer implemented method for providing cryptographic protection of data, comprising a memory with one or more instructions and a processor to implement the instructions to perform the steps of:
(A) reading or writing said data in a first memory circuit to or from a host;
(B) enabling or disabling a number of multipliers of a plurality of arithmetic modules in response to control signals received from said first memory circuit to implement a public key, wherein the number of multipliers enabled or disabled is proportional to a size of said public key; and
(C) reading or writing said data in a second memory circuit to or from said first memory circuit through a data exchange layer with a separate read channel and a separate write channel, wherein said arithmetic modules provide cryptographic protection of said data by generating results of two or more arithmetic operations to implement said public key.
20. An apparatus comprising:
a driver for reading or writing data in a first memory circuit to or from a host;
one or more hardware accelerators communicatively coupled to said driver and configured to enable or disable a plurality of arithmetic modules in response to control signals received from said first memory circuit; and
one or more bus networks for reading or writing said data in a second memory circuit to or from said first memory circuit through a data exchange layer having separate read and write channels, wherein said arithmetic modules provide cryptographic protection of said data by computing two or more arithmetic operations to authenticate a public key, and wherein said data exchange layer comprises a tree of data exchange layers corresponding to said plurality of arithmetic modules.