Three-dimensional semiconductor device
A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a multilayered structure by alternately stacking first material layers and second material layers on a substrate, wherein the second material layers are formed in a word line region and in a select line region. the select line region being located above the word line region;
forming etch stop patterns on the multilayered structure, wherein the etch stop patterns come into contact with an uppermost layer of the second material layers;
forming channel holes by etching the multilayered structure using the etch stop patterns as an etch barrier;
forming channel layers on surfaces of the channel holes;
filling the channel holes and a space between the etch stop patterns with insulating layers;
forming recessed regions between the etch stop patterns by recessing the insulating layers;
forming impurity-doped layers inside the recessed regions; and
forming an interlayer dielectric layer over the impurity-doped layers and the etch stop patterns.
2. The method of claim 1 , wherein bottom surfaces of the recessed regions are formed higher than a bottom surface of the uppermost layer, which is one of the second material layers.
3. The method of claim 1 , wherein the first material layers are insulating layers, and
the second material layers are conductive layers.
4. The method of claim 1 , wherein the first material layers are insulating layers, and
the second material layers are sacrificial layers.
5. The method of claim 4 , further comprising:
forming a slit through the multilayered structure after the interlayer dielectric layer is formed;
removing the second material layers exposed via the slit; and
filling regions from which the second material layers are removed with a conductive layer.
6. The method of claim 1 , wherein the second material layers, formed in the select line region, are thicker than the second material layers in the word line region.
7. The method of claim 1 , wherein the interlayer dielectric layer is thicker than either one of the first material layers, formed between the second material layers in the word line region, or each of the impurity-doped layers.
8. The method of claim 1 , further comprising:
forming a pipe gate layer on the substrate;
forming trenches in the pipe gate layer; and
filling the trenches with a sacrificial layer, and
where the multilayer structure is formed on the pipe gate layer and the sacrificial layer.
9. The method of claim 8 , wherein forming the channel holes exposes the sacrificial layer.
10. The method of claim 9 , wherein forming the channel layer further comprises:
removing, from the trenches, the sacrificial layer exposed via the channel holes; and
forming the channel layer in the trenches.
11. The method of claim 1 , wherein the etch stop patterns are nitride layers.