Receiver architecture for memory reads
A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.
1. A memory interface, comprising:
a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels;
a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels; and
a plurality of flip-flops located in close proximity to the plurality of receivers, wherein each of the flip-flops is configured to capture data from an output of a respective one of the plurality of receivers;
wherein the plurality of receivers and the plurality of flip-flops are all grouped together into a receiver subsystem that is located away from the plurality of transmitters, the plurality of transmitters span a first distance, the receiver subsystem spans a second distance, and the first distance is at least five times longer than the second distance.
2. The memory interface of claim 1 , wherein the plurality of receivers comprise at least eight receivers, and the plurality of receivers span a distance of 200 μm or less.
3. The memory interface of claim 2 , wherein the plurality of transmitters comprise at least eight transmitters, and the plurality of transmitters span a distance of at least 1 mm.
4. The memory interface of claim 1 , further comprising a plurality of low-impedance paths, wherein each of the low-impedance paths is configured to couple one of the plurality of receivers to the respective one of the plurality of I/O channels.
5. The memory interface of claim 4 , wherein each of the low-impedance paths is configured to be driven by a respective one of a plurality of transmitters of the memory device, and the memory interface and the memory device are located on different chips.
6. The memory interface of claim 5 , wherein each of the transmitters has an impedance of 100 ohms or less.
7. The memory interface of claim 5 , wherein each of the plurality of transmitters of the memory interface is configured to drive a respective one of a plurality of receivers of the memory device.
8. The memory interface of claim 4 , wherein each of the low-impedance paths is implemented using a redistribution layer (RDL) of a chip.
9. The memory interface of claim 1 , further comprising:
a strobe receiver configured to receive a data strobe signal from the memory device; and
a delay device configured to delay the received data strobe signal;
wherein each of the plurality of flip-flops is configured to capture data from the output of the respective one of the plurality of receivers using the delayed data strobe signal.
10. The memory interface of claim 1 , further comprising:
a strobe receiver configured to receive a data strobe signal from the memory device; and
a delay device configured to delay the received data strobe signal;
wherein each of the plurality of flip-flops is configured to capture data from the output of the respective one of the plurality of receivers using the delayed data strobe signal, and each of the plurality of transmitters is configured to drive the respective one of the plurality of I/O channels with data.
11. A method for transferring data, comprising:
transmitting data to a memory device over a plurality of I/O channels using a plurality of transmitters;
receiving data from the memory device over the plurality of I/O channels using a plurality of receivers, wherein each of the plurality of I/O channels is coupled to a respective one of the plurality of transmitters and a respective one of the plurality of receivers; and
capturing data from outputs of the plurality of receivers using a plurality of flip-flops located in close proximity to the plurality of receivers;
wherein the plurality of receivers and the plurality of flip-flops are all grouped together into a receiver subsystem that is located away from the plurality of transmitters, the plurality of transmitters span a first distance, the receiver subsystem spans a second distance, and the first distance is at least five times longer than the second distance.
12. The method of claim 11 , wherein receiving the data from the memory device over the plurality of I/O channels comprises receiving the data over a plurality of low-impedance paths coupled between a plurality of I/O contacts and the plurality of receivers, wherein the plurality of I/O contacts are coupled to the plurality of I/O channels, and the plurality of I/O contacts and the plurality of receivers are located on the same chip.
13. The method of claim 12 , wherein each of the low-impedance paths is driven by a respective one of a plurality of transmitters of the memory device.
14. The method of claim 12 , wherein each of the low-impedance paths is implemented using a redistribution layer (RDL) of the chip.
15. The method of claim 11 , further comprising:
receiving a data strobe signal from the memory device;
delaying the received data strobe signal; and
capturing data from the outputs of the plurality of receivers using the plurality of flip-flops and the delayed data strobe signal.