3D variable resistance memory device having junction FET and driving method thereof
A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.
1. A variable resistance memory device, comprising:
a semiconductor substrate;
a string selection switch formed on the semiconductor substrate;
a channel layer formed on the column string selection switch;
a plurality of gates stacked along a length of the channel layer, wherein each of the gates contacts an outer side of the channel layer; and
a variable resistance layer formed on an inner side of the channel layer, wherein the variable resistance layer contacts the channel layer.
2. The variable resistance memory device of claim 1 , wherein the string selection switch includes:
a common source region formed on the semiconductor substrate;
a channel pillar formed on the common source region;
a drain region formed in an upper portion of the channel pillar;
a gate surrounding an outer circumference of the channel pillar; and
a gate insulating layer interposed between the channel pillar and the gate.
3. The variable resistance memory device of claim 2 , further comprising:
an ohmic layer formed on the drain region.
4. The variable resistance memory device of claim 1 , wherein the plurality of gates are alternately stacked with a plurality of insulation layers.
5. The variable resistance memory device of claim 1 , wherein the plurality of gates are formed of a semiconductor layer having a first conductivity type, and the channel layer is formed of a semiconductor layer having a second conductivity type that is opposite the first conductivity type.
6. The variable resistance memory device of claim 1 , wherein the channel layer has a tubular shape, and the variable resistance layer is formed along an inner wall of the channel layer.
7. The variable resistance memory device of claim 6 , wherein a reverse bias is applied to a selected gate among the stacked gates and data is stored in the variable resistance layer facing the selected gate.
8. The variable resistance memory device of claim 1 , wherein the variable resistance layer includes:
a PCMO [spell out full name] layer, which is a material for a resistance random access memory (ReRAM),
a chalcogenide layer, which is a material for a phase-change RAM (PCRAM),
a magnetic layer, which is a material for a magnetic RAM (MRAM),
a magnetization reversal device layer, which is a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), and
a polymer layer, which is a material for a polymer RAM (PoRAM).