IP Library › Granted Patent US 9,214,395
Granted Patent B2
US 9,214,395 · App. 13/802,542 · Granted Dec 15, 2015

Method of manufacturing semiconductor devices

Inventors: Yu-Hsiang Hung (Tainan, TW); Chung-Fu Chang (Tainan, TW); Chia-Jong Liu (Ping-Tung County, TW); Yen-Liang Wu (Taipei, TW); Pei-Yu Chou (Tainan, TW); Home-Been Cheng (Keelung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/823814H01L21/823807H01L29/6656H01L29/66636H01L29/7834H01L29/7847H01L29/7848H01L29/165H01L29/665H01L29/66545
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Quick Facts
Patent No.
US 9,214,395
App. No.
13/802,542
Granted
Dec 15, 2015
Kind
B2
Abstract

A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Claims (27)

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a substrate having first type semiconductor regions and second type semiconductor regions, wherein said first type semiconductor region and said second type semiconductor region are provided respectively with at least one gate structure;

forming a first epitaxy mask layer conformally on said gate structures and said substrate;

removing a part of said first epitaxy mask layer on said first type semiconductor region and forming a first type epitaxial layer in said substrate at both sides of each said gate structure in said first type semiconductor region;

forming a second epitaxy mask layer conformally on said gate structures, said first type epitaxy layers and said substrate, wherein said second epitaxy mask layer covers on said first epitaxy mask layer on said second type semiconductor regions;

forming a second type epitaxial layer in said substrate at both sides of each said gate structure in said second type semiconductor region; and

removing said second epitaxy mask layer.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming said first type epitaxial layers comprises:

forming first epitaxy recesses in said substrate at both sides of each said gate structure in said first type semiconductor region; and

forming said first type epitaxial layer in each said first epitaxy recess.

3. A method of manufacturing a semiconductor device according to claim 2 , wherein the step of forming said first epitaxy recesses comprises:

forming a photoresist layer on said second type semiconductor regions; and

performing an etch process with said photoresist layer as an etch mask to remove a part of said first epitaxy mask layer and a part of said substrate in said first type semiconductor region, thereby forming said first epitaxy recesses, and the remaining said first epitaxy mask layer becomes spacers of said gate structures in said first type semiconductor region.

4. A method of manufacturing a semiconductor device according to claim 3 , wherein the steps of forming said first type epitaxial layers comprise: performing an epitaxial process with said spacers on said first type semiconductor region and said first epitaxy mask layer on said second type semiconductor region as an epitaxy mask to form said first type epitaxial layer in each said first epitaxy recess.

5. A method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming said second type epitaxial layers comprises:

forming second epitaxy recesses in said substrate at both sides of each said gate structure in said second type semiconductor region; and

forming said second type epitaxial layer in each said second epitaxy recess.

6. A method of manufacturing a semiconductor device according to claim 5 , wherein the steps of forming said second epitaxy recess further comprise:

forming a photoresist layer on said first type semiconductor region; and

performing an etch process with said photoresist layer as an etch mask to remove said second epitaxy mask layer and a part of said first epitaxy mask layer and a part of said substrate in said second type semiconductor region, thereby forming said second epitaxy recesses, and the remaining said first epitaxy mask layer becomes spacers of said gate structures in said second type semiconductor region.

7. A method of manufacturing a semiconductor device according to claim 6 , wherein the step of forming said second type epitaxial layers further comprises performing an epitaxial process with said second epitaxy mask layer on said first type semiconductor region and said spacers on said second type semiconductor region as epitaxy masks to form said second type epitaxial layer in each said second epitaxy recess.

8. A method of manufacturing a semiconductor device according to claim 1 , wherein said substrate further comprises third semiconductor regions with said gate structures, and said first epitaxy mask layer covers said third semiconductor region, and said first epitaxy mask layer further comprises an upper mask layer and a lower mask layer, and said method of manufacturing a semiconductor device after removing said second epitaxy mask layer further comprises:

forming a photoresist layer on said first type semiconductor region and said second type semiconductor region; and

performing an etch process with said photoresist layer as an etch mask and said lower mask layer as an etch stop layer to remove a part of said first epitaxy mask layer on said third semiconductor region, so that the remaining said first epitaxy mask layer becomes spacers of said gate structures in said third type semiconductor region.

9. A method of manufacturing a semiconductor device according to claim 1 , wherein the step after removing said second epitaxy mask layer further comprises:

forming a conformal layer on said substrate and said gate structures; and

performing at least one ion implantation process to form source/drain regions respectively at both sides of each said gate structures, wherein said first epitaxy mask layer and said conformal layer on sidewalls of said gate structure defines the distance between said gate structure and said source/drain regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2013
From: HUNG, YU-HSIANG; CHANG, CHUNG-FU; LIU, CHIA-JONG; WU, YEN-LIANG; CHOU, PEI-YU; CHENG, HOME-BEEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 029991/0238 →
Continuity (1)
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