Bias-boosting bias circuit for radio frequency power amplifier
Various embodiments provide a bias circuit for a radio frequency (RF) power amplifier (PA) to provide a direct current (DC) bias voltage, with bias boosting, to the RF PA. The bias circuit may include a bias transistor that forms a current mirror with an amplifier transistor of the RF PA. The bias circuit may further include a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor. The bias circuit may further include a second resistor coupled between the drain terminal of the bias transistor and the RF PA (e.g., the gate terminal of the amplifier transistor). An amount of bias boosting of the DC bias voltage provided by the bias circuit may be based on an impedance value of the second resistor.
1. A circuit comprising:
a radio frequency (RF) power amplifier to amplify an RF input signal, the RF power amplifier having an amplifier transistor with a gate terminal configured to receive the RF input signal;
a bias circuit coupled with the gate terminal of the amplifier transistor, the bias circuit to provide a direct current (DC) bias voltage at the gate terminal of the amplifier transistor wherein the bias circuit includes:
a bias transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the bias transistor coupled with the gate terminal of the amplifier transistor to form a current mirror;
a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor; and
a second resistor coupled between the drain terminal of the bias transistor and the gate terminal of the amplifier transistor, wherein an amount of bias boosting of a direct current (DC) bias voltage provided by the bias circuit is based on an impedance value of the second resistor,
wherein the bias circuit further includes a Wilson current mirror that includes the bias transistor.
2. The circuit of claim 1 , further comprising a capacitor coupled between the gate terminal of the bias transistor and a ground potential to provide a discharge path for RF signals.
3. The circuit of claim 1 , further comprising a current source coupled with the drain terminal of the bias transistor.
4. The circuit of claim 3 , wherein the impedance value of the second resistor is 1/100 or less of an impedance value of the current source.
5. The circuit of claim 1 , wherein the RF power amplifier is a complementary metal-oxide-semiconductor (CMOS) amplifier.
6. The circuit of claim 1 , wherein the bias transistor is to increase the DC bias voltage as an RF power of the RF input signal amplified by the RF amplifier increases.
7. A system comprising:
a radio frequency (RF) power amplifier to amplify an RF input signal, the RF power amplifier having a first amplifier transistor with a gate terminal to receive the RF input signal, wherein the RF power amplifier is a complementary metal-oxide-semiconductor (CMOS) amplifier, and wherein the RF power amplifier is a stacked power amplifier further including a second amplifier transistor having a source terminal coupled with a drain terminal of the first amplifier transistor;
a bias circuit coupled with the gate terminal of the first amplifier transistor, the bias circuit to provide a direct current (DC) bias voltage at the gate terminal of the first amplifier transistor, wherein the bias circuit includes:
a bias transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the bias transistor coupled with the gate terminal of the first amplifier transistor to form a current mirror;
a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor;
a capacitor coupled between the gate terminal of the bias transistor and a ground potential to provide a discharge path for RF signals; and
a second resistor coupled between the drain terminal of the bias transistor and the gate terminal of the first amplifier transistor;
wherein the bias circuit is configured to increase the DC bias voltage as an RF power of an RF input signal amplified by the RF amplifier increases, wherein an amount of the increase of the DC bias voltage is based on an impedance value of the second resistor.
8. The system of claim 7 , wherein the bias circuit further includes a current source coupled with the drain terminal of the bias transistor.
9. The system of claim 8 , wherein the impedance value of the second resistor is 1/100 or less than an impedance value of the current source.
10. The system of claim 7 , wherein the bias circuit further includes a diode-connected transistor coupled with the drain of the bias transistor to provide additional bias boosting.
11. The system of claim 7 , wherein the bias circuit further includes a Wilson current mirror that includes the bias transistor.
12. The system of claim 7 , further comprising a transmitter coupled with the RF power amplifier to provide the RF input signal to the RF power amplifier.
13. A system comprising:
a radio frequency (RF) power amplifier to amplify an RF input signal, the RF power amplifier having an amplifier transistor with a gate terminal to receive the RF input signal;
a bias circuit coupled with the gate terminal of the amplifier transistor, the bias circuit to provide a direct current (DC) bias voltage at the gate terminal of the amplifier transistor, wherein the bias circuit includes:
a bias transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the bias transistor coupled with the gate terminal of the amplifier transistor to form a current mirror;
a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor;
a capacitor coupled between the gate terminal of the bias transistor and a ground potential to provide a discharge path for RF signals;
a second resistor coupled between the drain terminal of the bias transistor and the gate terminal of the amplifier transistor; and
a diode-connected transistor coupled with the drain of the bias transistor to provide additional bias boosting;
wherein the bias circuit is configured to increase the DC bias voltage as an RF power of an RF input signal amplified by the RF amplifier increases, wherein an amount of the increase of the DC bias voltage is based on an impedance value of the second resistor.
14. The system of claim 13 , wherein the bias circuit further includes a current source coupled with the drain terminal of the bias transistor.
15. The system of claim 14 , wherein the impedance value of the second resistor is 1/100 or less than an impedance value of the current source.
16. A system comprising:
a radio frequency (RF) power amplifier to amplify an RF input signal, the RF power amplifier having an amplifier transistor with a gate terminal to receive the RF input signal;
a bias circuit coupled with the gate terminal of the amplifier transistor, the bias circuit to provide a direct current (DC) bias voltage at the gate terminal of the amplifier transistor, wherein the bias circuit includes:
a bias transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the bias transistor coupled with the gate terminal of the amplifier transistor to form a current mirror;
a first resistor coupled between the gate terminal and the drain terminal of the bias transistor to block RF signals from the gate terminal of the bias transistor;
a capacitor coupled between the gate terminal of the bias transistor and a ground potential to provide a discharge path for RF signals; and
a second resistor coupled between the drain terminal of the bias transistor and the gate terminal of the amplifier transistor;
wherein the bias circuit is configured to increase the DC bias voltage as an RF power of an RF input signal amplified by the RF amplifier increases, wherein an amount of the increase of the DC bias voltage is based on an impedance value of the second resistor; and
wherein the bias circuit further includes a Wilson current mirror that includes the bias transistor.
17. The system of claim 16 , wherein the bias circuit further includes a current source coupled with the drain terminal of the bias transistor.
18. The system of claim 17 , wherein the impedance value of the second resistor is 1/100 or less than an impedance value of the current source.
19. The system of claim 16 , wherein the RF power amplifier is a complementary metal-oxide-semiconductor (CMOS) amplifier.