Semiconductor memory device

1. A semiconductor memory device, comprising:

a memory device configured having memory cells arranged therein;

a data output buffer for outputting data read from the memory device, and a data input buffer for receiving data to be written to the memory device;

a plurality of input/output pads to which the data input buffer and the data output buffer for inputting/outputting the data are respectively connected;

a plurality of on-die termination circuits each connected to any one of the plurality of input/output pads; and

a control circuit operative to control the on-die termination circuits,

the plurality of on-die termination circuits each comprising:

a pull-up element connected between a first terminal and an output terminal; and

a pull-down element connected between the output terminal and a second terminal,

the pull-up element being driven by a first pull-up element driver,

the pull-down element being driven by a first pull-down element driver, and

the control circuit being operative to activate a plurality of the on-die termination circuits at different timings,

wherein at least a portion of the plurality of on-die termination circuits function also as an off-chip driver circuit for when outputting data from the memory cell array to external,

and further comprising:

a second pull-up element driver for driving the pull-up element when the on-die termination circuit is caused to function as the off-chip driver circuit; and

a second pull-down element driver for driving the pull-down element when the on-die termination circuit is caused to function as the off-chip driver circuit.

2. The semiconductor memory device according to claim 1 , wherein

the control circuit is configured to transmit to the first pull-up element driver and the first pull-down element driver a first activating signal which is for activating the plurality of the on-die termination circuits at different timings.

3. The semiconductor memory device according to claim 1 , wherein

the control circuit is configured to transmit to the first pull-up element driver and the first pull-down element driver a second activating signal which is configured through-rate changeable.

4. The semiconductor memory device according to claim 1 , wherein

the control circuit is configured to

transmit to the first pull-up element driver and the first pull-down element driver a first activating signal which is for activating the plurality of the on-die termination circuits at different timings, and

transmit to the first pull-up element driver and the first pull-down element driver a second activating signal which is configured through-rate changeable.

5. The semiconductor memory device according to claim 4 , wherein

the first pull-up element driver and the first pull-down element driver are configured having a first p type MOS transistor, a first n type MOS transistor, and a first transistor connected in series therein,

gates of the first p type MOS transistor and the first n type MOS transistor are inputted with the first activating signal, and

a gate of the first transistor is inputted with the second activating signal.

6. The semiconductor memory device according to claim 1 , wherein

a plurality of the on-die termination circuits are connected to a single one of the input/output pads, and

the control circuit is configured to selectively drive at least one or multiple ones of a plurality of the on-die termination circuits to provide a different termination resistance to the input/output pad.

7. The semiconductor memory device according to claim 1 , wherein

the second pull-up element driver and the second pull-down element driver are configured having a second p type MOS transistor, a second n type MOS transistor, and a second transistor connected in series therein,

gates of the second p type MOS transistor and the second n type MOS transistor are inputted with the third activating signal, and

a gate of the second transistor is inputted with the fourth activating signal.

8. The semiconductor memory device according to claim 1 , wherein

a plurality of the on-die termination circuits are connected to a single one of the input/output pads, and

the control circuit is configured to selectively drive at least one or multiple ones of a plurality of the on-die termination circuits to provide a different termination resistance to the input/output pad.

9. The semiconductor memory device according to claim 1 , wherein

the first pull-up element driver and the first pull-down element driver are activated at timings that differ from each other.

10. The semiconductor memory device according to claim 1 , wherein

the pull-up element includes a third transistor and a first resistance connected in series, and

the pull-down element includes a fourth transistor and a second resistance connected in series.

11. A semiconductor memory device, comprising:

a memory device configured having memory cells arranged therein;

a data output buffer for outputting data read from the memory device, and a data input buffer for receiving data to be written to the memory device;

a plurality of input/output pads to which the data input buffer and the data output buffer for inputting/outputting the data are respectively connected;

a plurality of on-die termination circuits and a plurality of off-chip driver circuits each connected to any one of the plurality of input/output pads; and

a control circuit operative to control the on-die termination circuit and the off-chip driver circuit,

the control circuit being configured to selectively drive at least one or multiple ones of the on-die termination circuits or the off-chip driver circuits to provide a different termination resistance to the input/output pad.

12. The semiconductor memory device according to claim 11 , wherein

a plurality of the on-die termination circuits connected to a single one of the plurality of input/output pads have different resistance values.

13. The semiconductor memory device according to claim 11 , wherein

a plurality of the off-chip driver circuits connected to a single one of the plurality of input/output pads have different resistance values.

14. The semiconductor memory device according to claim 11 , wherein

a plurality of the on-die termination circuits connected to a single one of the plurality of input/output pads have different resistance values, and

a plurality of the off-chip driver circuits connected to a single one of the plurality of input/output pads have different resistance values.

15. The semiconductor memory device according to claim 11 , wherein

at least one of the on-die termination circuits is a dual-purpose circuit that doubles as an off-chip driver circuit.

16. The semiconductor memory device according to claim 15 , further comprising a selection circuit operative to select the dual-purpose circuit,

wherein the selection circuit activates the dual-purpose circuit as an on-die termination circuit or as an off-chip driver circuit in accordance with an enable signal instructing whether to select the dual-purpose circuit as the on-die termination circuit or whether to select the dual-purpose circuit as the off-chip driver circuit.